Abstract-We have developed a novel and practical virtual cell designing environment. For the practical use, the system provides simulators highly calibrated and adaptive to new structure devices and processes; tools for analyzing the effect of process variations on device characteristics or parasite capacitance; and easy-to-use GUI. This environment is used in practical work and has reduced TAT of cell designing to less than one eighth: Furthermore, it has enabled evaluation of even new structured devices

Hajime Takaaki Tatsumi

Komatsu

Mikio Nakayama

Yasutoshi Mukai

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7-1 6 
Practical Virtual Cell Designing Environment 
. Takaaki Tatsumi, Hajime Nakayama, Mikio Mukai and Yasutoshi Komatsu 
LSI Business and Technology Development Group, CNC, Sony Corporation 
4-14-1 Asahi-cho, Atsugi-shi, Kanagawa-ken, 243-0014 Japan 
Tel: +81-46-230-5719, Fax: +81-46-230-5572, e-mail: tatsumi@ulsi.sony.co.jp 
Abstract- We have developed a novel and practical 
virtual cell designing environment. For the practical 
use, the system provides simulators highly calibrated 
and adaptive to new structure devices and processes; 
tools for analyzing the effect of process variations 
on device characteristics or parasite capacitance; and 
easy-to-use GUI. This environment is used in practi- 
cal work and has reduced TAT of cell designing to less 
than one eighth: Furthermore, it has enabled evalua- 
tion of even new structured devices. 
I. INTRODUCTION 
The realization of virtual cell designing environment, in 
which a series of operations from transistor designing to 
cell verification are done only by computer simulations, is 
an essential factor for concurrent designing of ULSI. How- 
ever, the virtual cell environment for practical use requires 
well-calibrated simulators and an easy-to-use interface for 
reliable result and efficient operation. This requirement 
caused the realization of virtual cell environment for prac- 
tical use very difficult. We have developed a virtual cell 
environment tolerable for daily work by device engineers. 
For the use of practical work, the 'system has following 
novel points: simulators are highly calibrated with refer- 
ring measured data stored in a database[l][2] and also 
very adaptive to new structure devices and new processes 
since the system is well established for tuning procedures; 
practical tools for analyzing the effect of process variations 
on device characteristics or parasite capacitance are pro- 
vided; to deal with the needs of increasing and spreading 
simulator users, user-friendly GUI (Graphical User Inter- 
face) is implemented on low-cost platforms. 
In this paper, after explaining the modules which con- 
sist the virtual cell environment, we will present an appli- 
cation example of utilizing this system for predicting the 
performance of 0.13pm generation MOSFET. 
' 
11. CHARACTERISTICS OF THE VIRTUAL CELL 
DESIGNING ENVIRONMENT 
Module structure of the virtual cell environment is 
shown on Fig.1. Electrical characteristics, such as thresh- 
old voltage (Vth) and saturation current, and transistor 
C-V characteristics are simulated with 2D process/device 
simulators. Interconnect capacitance is calculated with 
3D capacitance simulator. SPICE parameters including 
I-V characteristics, C-V characteristics and interconnect 
capacitance are extracted from these calculation results 
and then the circuit characteristics are analyzed. ~ 
A. Process/Device Simulation Module 
In this module, 2D process and device simulations are 
performed to extract the electrical and C-V characteris- 
tics[3]. The novel points of this module are as follows: 
(1)Both of process and device simulators are highly cali- 
brated by referring measured data stored in a database, 
which enables accurate prediction of the effect on device 
characteristics for variations of process conditions; (2)The 
effect of process variations on device characteristics can 
be specified and automatically simulated. Any process 
parameters, including mask dimension, such as gate mask 
length and sidewall mask length, can be specified with an 
easy-to-use GUI. Also, when more than two process vary 
according to Gauss distribution, the effect can be pre- 
dicted with less than 1/100 times calculations compared 
with Monte Carlo method; (3)According to the transis- 
tor type of P-ch or N-ch, and characteristics to be calcu- 
lated, such as Id-Vg, Id-Vd, Cgs-Vg etc., well-calibrated 
parameters are automatically specified. Furthermore, pa- 
rameters or mesh structures for new type devices can be 
efficiently specified with GUI, which assists not only de- 
signing work by device engineers but also tuning of simu- 
lators by TCAD engineers. 
\ 
B. Interconnect Capacitance Simulation Module 
To extract SPICE parameters including interconnect 
capacitance and net-list, 3D simulation of interconnect 
capacitance is performed with this module[4,5,6], with the 
input of GDS-I1 formatted mask data. The novel point 
of this module is that the variation of mask dimension 
such as magnification and reduction, deviation of its po- 
sition, and other process parameters such as thickness of 
the films and permittivity ratio, can be easily specified 
with GUI and simulated. Fig.2 shows this module being 
operated. Masks of a buffer cell are shown and an input 
panel for specifying interconnect thickness is exposed at 
the upper half of the figure. Input data files for the simu- 
163 
SPICE Parameter 1-11 + Extract or 
I-V spec. 
C-V spec. 
Circuit Analysis 
Net - 1 is t 
cell design environment 
Fig.1 Module structure of the virtual 
lator, which correspond to the specification are automat- 
ically synthesized and then calculated. The, lower halves 
of fig.2 are the result of mask shapes when interconnect 
width is reduced or magnified by 0.05pm to both X and Y 
directions. Table 1 shows the comparison of capacitance 
for each interconnect conditions to the original. 
111. IMPLEMENTATION AND USE OF THE SYSTEM 
To deal with the needs of increasing and spreading sim- 
ulator users, this virtual cell designing environment is 
used under server-client environment, which enables ”re- 
mote simulation” on low-cost platforms[7]. Client pro- 
gram, which is GUI program for users’ data operation, 
is written with JAVA. Simulator users access this virtual 
cell environment from WWW browser via WWW server. 
This mechanism enables engineers to use the newest pro- 
gram version and reduces the amount of data transfer a 
lot compared with remote login use. 
IV. APPLICATION EXAMPLE 
In the development of 0.13pm generation MOSFET 
device, device characteristics are calculated utilizing the 
virtual cell designing environment to predict the perfor- 
mance before manufacturing and then compared with the 
measured characteristics of test chips manufactured with 
the predicted process conditions. Fig.3 is the cell layout of 
the tested inverter forming a ring-oscillator for delay and 
power estimation. An equivalent circuit of it is shown in 
fig.4. The god of this simulation is to predict threshold 
voltage (Vth) roll-off curve and delay vs power character- 
istics. 
Utilizing the virtual cell environment, a series of simula- 
tions are performed and SPICE parameters are extracted 
from the results. Firstly, two dimensional process sim- 
ulation is performed. Fig.5 shows BF2 distribution, im- 
planted to S/D, to depth direction and fig.6 parallel to 
surface. Three kinds of implantation energy is simulated 
to evaluate the effect of it. By using GUI provided in this 
system, process variations are easily specified, simulated 
and visualized. 
Device simulations are then performed with the result 
of process simulation. Fig.7 is a graph of junction capac- 
Fig. 2 Original mask for intercon- 
nect (upper) and the result of devi- 
ating width (lower left: thinner, 
right : thicker) 
Table 1 Effect of ,interconnect 
width deviation on interconnect 
capacitance (unit: F) 
164 
IN-A 
IN- B 
. . .  . . .  . . .  . . .  . . .  . . .  . . .  . . .  . . . .  . . .  . . .  
. . .  . . .  . . .  . . .  
7 -  . . .  . . .  . . .  . . .  . . ,  . . .  . . .  . . .  
. . .  -
- - - 
Fig. 3 Cell layout of the tested 
inverter 
itance vs drain voltage. Once specified in process simula- 
tion, three conditions of implantation energy in this case 
are simulated automatically. Fig.8 is a drain current vs 
gate voltage (Id-Vg). Three kinds of dosage for Boron, 
the ion for threshold voltage adjustment ion implantation 
process, are simulated here. Fig.9 is the graph of Vth roll- 
off curve for calculated and measured MOS device. X-axis 
stands for gate length and Y-axis for threshold voltage. 
This result shows fairly good match between simulated 
and measured data. 
Utilizing the electrical characteristics simulated above 
and interconnect capacitance which is also simulated with 
this system, the performance of the devices are analyzed 
with the circuit analysis engine SPECTRE[8]. Fig.10 is 
the comparison of delay (X-axis) vs power (Y-axis) de- 
pendence. In this case, to evaluate it on measured data, 
SPICE parameters are extracted from manufactured test 
chips and simulated utilizing the virtual cell designing en- 
vironment. The simulation results also showed quite good 
agreement with measurement. 
Even for the user who is not an expert of simulation, 
it took only one week for this analysis. By utilizing this 
system, the time for evaluation of new process is reduced 
to one eighth or less compared with test manufacturing 
which usually requires two to three months or more. 
V. SUMMARY AND CONCLUSIONS 
i 
We have developed a novel and practical virtual cell de- 
signing environment which provides well-calibrated sim- 
ulator and easy-to-use GUI. This environment is used in 
practical work and has reduced TAT of cell designing to 
less than one eighth and enabled evaluation of even new 
IN-A 
IN-B 
OUT 
4 5  
vss 
Fig. 4 Equevalent circuit of the cell 
layout shown in fig.3 
structured devices. 
REFERENCES 
T. Tatsumi et al., “MOSQue : A Novel TCAD Database System 
with Efficient Handling Capability on Measured and Simulated 
Data,” Proc. SISPAD’97, pp.265-268, 1997. 
M.Mukai et al., “Increased Simulation Accuracy Based on 
Merged Process Device Simulation System and Database Tool,” 
Extended Abstract of the 45th JSAP Spring Meeting, 28p-L-6, 
1998. 
T. Tatsumi, H. Ansai, K .  Hayakawa and M. Mukai, “BARAS 
: Novel and Highly Efficient Simulation System for Process 
Control Sweeping and Statistical Variation,” Proc SISPAD’96, 
pp. 149- 150, 1996. 
M.Mukai et al., “The simulation system for three-dimensional 
capacitance and current density calculation with a user friendly 
GUI,” SISDEP Vol. 6, pp. 151-154, Springer-Verlag, 1995. 
R.Bauer et al., “Capacitance calculation of VLSI multilevel 
wiring structures,” Proc. VPAD workshop, pp.142-143, 1993 
RSabelka, K.Koyama and S.Selberherr, “STAP - A finite ele- 
ment simulator for three-dimensional thermal analysis of inter- 
connect structures,” Proc. European Simulation Symposium, 
pp.621-625, 1997 
K.Yoshitomi, T.Tatsumi, N.Nakauchi, M.Mukai and 
Y .Komatsu, “NILE: A novel platform-independent and efficient 
distributed simulation system for TCAD,” Proc. SISPAD’99 (in 
press) 
“SPECTRE Product Manual,” ‘Cadence, 1998. 
165 
1 
h ‘  
E 
Y 
1 OZ1 
l o z o  
1 o i9  
1 
1 o i7  
1 O i 6  
0.0 0 1  0 2  0.3 0.4 0 5  
‘ Depth (Fm) 
Fig.5 BF2 distribution (depth) 
with three variation of implan- 
tation energy 
E LL 
E 
v 
. t  
0 
0 r 
.- 
U 
-0.5 -1.0 -1.5 -2.0 
Drain Voltage Vdb (V) 
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Fig.7 Junction capacitance vs 
drain voltage with three varia- 
tions of BF2 implantation energy 
h > 
W 
2 
0 
L cn a 
0.5 
0.45 
0.4 
0.35 
0.3 
0.25 
0.2 i , , , , ~  , , , ,  i , , , ,  
0.1 . 0.2 0.3 ‘0.4 0.5 
Gate Length (pm) 
Fig.9 Threshold voltage (Vth) 
roll-off curve 
1021 
Y - 
w 
-0.3 -0.2 -0.1 0.0 0.1 0 .2  0.3 
Distance (pm) 
Fig.6 BF2 distribution (surface) 
with three variations of implan- 
tation energy 
h 
E 
3 
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E 
1 0 -2 
l o 4  
10” 
l o 4  
10-”0 
10 -I2 
0.0 0 3  0.6 0.9 1.2 15 1.8 
vg (V) 
Fig.8 Drain current,vs gate voltage 
with three variations of BF2 implan- 
tation energy 
2 c 
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$ 0
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2 5  
2 0  
15 
10 
5 
0 
0 10 2 0  30 4 0  5 0  6 0  7 0  8 0  
Delay ( P a  
Fig.10 Delay vs power calcu- 
lated from simulated and 
measured data 
166 


Practical Virtual Cell Designing Environment

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