ABSTRACT 1 This paper presents a low-power structure of digital matched filters (DMFs), which is proposed for direct sequence spread spectrum systems. Traditionally, low-power approaches for DMFs are based on either the transposedform structure or the direct-form one. A new hybrid structure that employs the direct-form structure for local addition and the transposed-form structure for global addition is used to take advantages of both structures. For a 128-tap DMF, the proposed DMF that processes 32 addends a cycle consumes 46 % less power at the expense of 6 % area overhead as compared to the state-of-the-art low-power DM

In-Cheol Park

Sung-Won Lee

CiteSeerX

 LOW-POWER HYBRID STRUCTURE OF DIGITAL MATCHED FILTERS 
FOR DIRECT SEQUENCE SPREAD SPECTRUM SYSTEMS 
 
Sung-Won Lee and In-Cheol Park 
 
Department of Electrical Engineering and Computer Science, KAIST 
373-1 Guseong-Dong Yuseong-Gu, Daejeon 305-701, Republic of Korea 
 
 
ABSTRACT1 
 
This paper presents a low-power structure of digital 
matched filters (DMFs), which is proposed for direct se-
quence spread spectrum systems. Traditionally, low-power 
approaches for DMFs are based on either the transposed-
form structure or the direct-form one. A new hybrid struc-
ture that employs the direct-form structure for local addi-
tion and the transposed-form structure for global addition 
is used to take advantages of both structures. For a 128-tap 
DMF, the proposed DMF that processes 32 addends a cy-
cle consumes 46 % less power at the expense of 6 % area 
overhead as compared to the state-of-the-art low-power 
DMF [7]. 
 
1. INTRODUCTION 
 
Direct sequence spread spectrum (DSSS) systems are the 
most popular wireless communication systems, and are 
being used for WLAN, IS-95, and WCDMA because of 
low power spectrum density and good resistance to multi-
path fading [1][2]. In the DSSS systems, matched filters 
(MFs) are widely employed for code acquisition, as they 
provide fast synchronization speed as well as reliable op-
eration. Other techniques such as non-correlation methods 
[3] or threshold decoding methods [4] do not provide 
competitive performance in real environment. 
Growing demands for portable, battery-powered sys-
tems necessitate low-power MFs to reduce the power con-
sumption of code acquisition circuits. Low-power MFs can 
be implemented by using either analog or digital technol-
ogy. For short and fast MFs, analog implementation is 
more power efficient than digital counterpart [5]. As 
CMOS technology advances rapidly and the reference 
code length in modern wireless communication systems 
increases, significant attention has focused on low-power 
digital matched filters (DMFs) [6-8]. 
Traditional low-power approaches for DMFs are based 
on either the transposed-form structure or the direct-form 
                                                 
This work was supported by the Korea Science and Engineering Founda-
tion through the MICROS center and IC Design and Education Center. 
structure. Due to the fast speed, low-power techniques 
such as differential coefficient scheme are first developed 
based on the transposed-form structure [6]. Although the 
schemes considerably save computation power, it is hard 
to reduce the large power consumed by memory elements 
that switch every cycle. As a result, the alternative direct-
form structure is considered later. The register file adopted 
for storing the input replaces the tapped delay line struc-
ture, resulting in a large saving of switching power. To 
further reduce power by minimizing the number of addi-
tions, the prefilter [7] is employed. Pipelined and parallel 
additions [7][8] are also considered to compensate the 
speed penalty induced by the direct-form structure. As the 
low-power approaches have been developed separately 
based on the two structures each of which considers only 
one of two extreme cases, one addition a cycle and all ad-
ditions a cycle, there are many chances to further reduce 
power by exploring the middle structure combining the 
two structures. 
To take advantages of both direct-form and transposed-
form structures, we propose in this paper a low-power 
DMF based on a new hybrid structure. Compared to the 
state-of-the-art low-power scheme [7], 46 % power is re-
duced at the area overhead of 6 %. 
 
2. LOW-POWER DIGITAL MATCHED FILTER 
 
An n-tap direct-form DMF is expressed as below 
 [ ] [ ]10
n
ii
y k c x k i−
=
= −∑  (1) 
where ci, 0 ≤ i < n, denotes the filter coefficients and x[i],  
i > 0, denotes the received signal. The transposed-form 
structure corresponding to the n-tap DMF is expressed as 
follows 
 
[ ] [ ]
[ ] [ ] [ ]
[ ] [ ]
1
1 1
1 , 1
n
i n i i
n
y k v k
v k c x k v k i n
v k c x k
− −
−
=
= + − < ≤
=
 (2) 
where vi[k] stores the intermediate result of output, y[k]. 
Based on (1) and (2), the direct-form and the transposed-
form implementations of a 4-tap DMF are derived as 
shown in Figure 1. The transposed-form structure accumu-
II - 8490-7803-7663-3/03/$17.00 ©2003 IEEE
This paper was originally published in the Proceedings of the 2003 IEEE
International Conference on Acoustics, Speech, & Signal Processing,
April 6-10, 2003, Hong Kong (cancelled). Reprinted with permission.
➠ ➡
lates the output every cycle. As the number of addends is 
much less than that of the direct-form structure, the trans-
posed-form structure can operate at a higher clock fre-
quency. On the other hand, the large fanout and registers 
updated every cycle lead to more power consumption. 
Both structures compute extreme cases, i.e., either one ad-
dend a cycle or n addends a cycle. A different number of 
addends in between one and n may produce more power-
efficient results. Nevertheless, this issue has not been dis-
cussed. 
 
2.1. Hybrid Structure 
 
To explore the middles between the two extreme structures, 
we modify the transposed form equation (2) to control 
number of addends in a cycle. Let s be the summation de-
gree that means the number of addends to be added in a 
cycle. Then n can be represented as s ×  t + r such that 1 < 
s < n, 0 < t, and 0 ≤ r < s where all s, t, and r are integers. 
The equation (2) can be rewritten as follows 
 
[ ] [ ] [ ]
[ ]
[ ]
[ ]
1
0
1
10
1
1 0
, 0
, 0
[ ] [ ] , 1
[ ]
r
j tj
t
s
i n s i j ij
s
n s jj
c x k j v k r r
y k
v k r
v k c x k j v k s i t
v k c x k j
−
=
−
− × + −=
−
− +=
 − + − ≠= 
=
= − + − < ≤
= −
∑
∑
∑
 (3) 
Based on (3), we propose a new hybrid structure for the 
DMF. As each vi[k] is computed by using the direct-form 
equation, we call this a local direct-form structure. All 
vi[k] share the input x[k - j], and thus we call this a global 
transposed-form structure. For example, a 4-tap DMF 
based on the hybrid structure with s = 2 is shown in Figure 
2. 
Compared to the conventional DMFs, the hybrid struc-
ture has several advantages as can be seen in Figure 2. For 
an output computation, the addition takes place at every s 
cycles, which implies a register file can replace the mem-
ory elements consuming a lot of power in order to reduce 
switching activities. In addition, carry-save addition can be 
accommodated without extra memory elements, and the 
number of input fanouts is reduced to 1/s of the initial 
value. Although the computation speed of the hybrid DMF 
is slower than that of the transposed-form DMF, it is still 
faster than the direct-form DMF. 
 
2.2. Applying the Differential Coefficient Scheme 
 
To reduce the number of computations in a DMF, the dif-
ferential coefficient scheme was proposed to exploit the 
run property of PN sequences was proposed [6]. By taking 
the difference between two consecutive filter coefficients 
as new coefficients, the output function in (1) can be 
modified as follows 
 
[ ] [ ]{ [ ]
[ ] [ ]} [ ]
[ ] [ ]
1 1 2
1 0 0
0
0 ( ) 1
( ) 1 1
1
n n n
n
ii
y n c x c c x
c c x n c x n y n
d x n i y n
− − −
=
= − + − + +
− − + + −
= − + −∑

 (4) 
where di, 0 ≤ i ≤ n, is the filter coefficient of the new DMF. 
From (4), d0 is c0, di, 0 < i < n, is ci – ci-1, and dn is –cn-1. 
Figure 3 shows the hybrid structure obtained by applying 
the differential coefficient scheme to the DMF shown in 
Figure 2. 
If the oversampling rate of a DMF is m, the number of 
multiplication and addition is reduced to 1/2m approxi-
mately by applying the differential coefficient scheme [6]. 
This reduction is very attractive in achieving low power 
consumption. Unfortunately, the differential coefficient 
scheme has not been employed in the current low-power 
DMFs because it draws more power in the direct-form 
structure [7][8]. However, as the proposed hybrid structure 
is globally transposed form structure, it is well fit for the 
differential coefficient scheme. 
 
2.3. Optimal Summation Degree s for Low Power 
 
The specification of a target DMF is needed to investigate 
the power characteristics of the proposed hybrid structure 
Dx
D D D
D D D D
c3 c2 c1 c0
y
y
c0 c1 c2 c3
(b) 4-tap transposed-form digital matched filter.
(a) 4-tap direct-form digital matched filter.
x
 
Figure 1. Conventional digital matched filter. 
Dx
D D
c2 c3 c0 c1
y
D
 
Figure 2. Proposed hybrid structure of digital matched filter.
Dx
D D
d3 d4 d1 d2
y
D
D D
d0
Figure 3. Hybrid digital matched filter employing differential 
coefficient scheme. 
Table 1. Key design parameters of the digital matched filter. 
Design parameter Value 
Input word length 4 bits 
Oversampling rate 4 samples/chip 
Tap number 128 taps 
II - 850
➡ ➡
by varying s. Three key design parameters of the DMF 
that are carefully determined are listed in Table 1. The 4-
bit input word length induces only a 0.1 dB performance 
loss in a scalar Gaussian channel at a marginal circuit 
complexity, and the oversampling rate of 4 is conservative 
and accurate enough for most applications [2]. The 128-
tap DMF performs coherent integration over a 32-chip in-
terval, which results in the processing gain of 15 dB. 
To determine the optimal summation degree s in terms 
of low power, a reference architecture that can be config-
ured with varying s is designed. Figure 4(a) shows the 
overall architecture, which mainly consists of an input re-
ceiving unit, an add unit, and a register file. The input re-
ceiving unit shown in Figure 4(b) exploits the fact that m 
consecutive filter coefficients are equal in an m oversam-
pling DMF. Under the differential coefficient scheme, the 
last m-1 coefficients become zero. Therefore, the first m 
input storing part is implemented with a register file in-
stead of shift registers to avoid unnecessary switching 
power consumption. The rest of the input storing part is 
implemented using shift registers that are activated every 
m cycles. 
The add unit employs a carry-save adder structure, 
which computes a number of addends as a whole at the 
cost of a little timing overhead and has a regular layout as 
well. How to perform 2’s complement signed addition in 
the add unit is presented in Figure 4(c). Among s/m ad-
dends, the addends with zero coefficient are omitted for 
the sake of less hardware and power saving. The sign bit 
inversion technique is used to reduce the hardware com-
plexity of sign extension. The complementary constant 
that can be determined earlier is subtracted from the result 
at the last addition step. Filter coefficients with minus sign 
need negation that is implemented by using 1’s comple-
ment numbers first and then adding 1s in the empty loca-
tion as in Figure 4(c) or in the last steps. By managing the 
empty locations that would be assigned to 1s, we can make 
this constant disjoint with the 4-bit value. Finally, register 
files are used to reduce the number of switching activities 
of flip-flops (FFs). 
The dynamic power consumption of the DMF is esti-
mated by using the following equation in [8] 
 
2
( ) ( )2
dd
i i j j
net i cell j
VP Cl Pn E Pc
∀ ∀
= ⋅ + ⋅∑ ∑  (5) 
where Cli and Pni are the total load capacitance and the 
switching probability for node i, Ej and Pcj are the internal 
energy and the switching probability of the output node for 
logic cell j, respectively. In the estimation, Cli and Ej are 
characterized in the technology library [9]. Pni and Pcj are 
obtained from the gate-level simulation.  
In Figure 5, the power consumption and the gate count 
of the hybrid DMF are compared with varying s. The gate 
count becomes smaller as the summation degree s in-
creases. On the other hand, the power consumption is op-
timal at s = 32 with a little area overhead. Therefore, the 
power-optimal s is set to 32 for the hybrid DMF. The final 
architecture is shown in Figure 6. 
 
3. EVALUATION 
 
To evaluate the performance of the proposed low-power 
DMF, we compare it with the state-of-the-art low-power 
DMFs found in the literature. Since other DMFs are de-
signed in different technologies and have different optimi-
zation levels, their architecture characteristics are ex-
tracted and redesigned with a standard cell library [9] in 
order to make the comparison fair. As the control part oc-
cupies a very small area and consumes a little power rela-
tively, it is not included in the comparison results summa-
rized in Table 2. 
In [7], the prefilter is employed to eliminate repeated 
identical additions. As a result, the number of total addi-
tions is reduced down to 1/m. A pipelined adder tree is 
used to boost the throughput. In [8], almost the same ar-
Input Receiving Unit
Add
Unit
Register
File
Add
Unit
D
FF
D
FF
(s/m) x 4 bits
4 bits
Input
11 bits
Output
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
Input
(s/m) x 4 bits
Sign extension /
Negation constant
Transform 1's complement into
2's complement for negation
(sign bit) for sign
extension Omit zero
coefficient term
Intermediate result
(a) Overall architecture.
(b) Details of the Input Receiving Unit.
(c) Signed addition in the Add Unit.
m
s entries
Figure 4. Reference architecture of hybrid digital matched filter 
with summation degree s. 
0.2
0.4
0.6
0.8
1
1.2
8 16 32 64
2
4.8
7.6
10.4
13.2
16
Gate Count
Power Consumption
Po
w
er
 C
on
su
m
pt
io
n 
(m
W
/M
H
z)
G
at
e 
Co
un
t (
K
 G
at
es
)
Summation Degree s
Po
w
er
 C
on
su
m
pt
io
n 
(m
W
/M
H
z)
G
at
e 
Co
un
t (
K
 G
at
es
)
 
Figure 5. Power consumption and area (gate count) of the hy-
brid digital matched filter with varying s = 8, 16, 32, or 64. 
II - 851
➡ ➡
chitecture as [7] is adopted except that m identical adder 
trees are used instead to enhance the throughput. In [6], 
the differential coefficient scheme is proposed and applied 
to the transposed-form DMF. However, the result is nei-
ther power efficient nor area efficient. As compared to the 
proposed DMF, it occupies 21 % more area and consumes 
7 times more power. Note that Liu’s and the proposed 
DMF (in part) are commonly based on the transposed-
form structure, but the number of switching FFs of the 
proposed is much smaller than that of Liu’s. Compared to 
Liou’s, the proposed scheme dissipates 46 % less power 
with 6 % of area overhead. On the other hand, Goto’s has 
35% area overhead and achieves 42 % power reduction. In 
addition, the proposed DMF has a comparable critical path 
delay to that of Liou’s and Goto’s without applying 
throughput-boosting schemes such as pipelining or parallel 
computing. 
 
4. CONCLUSIONS 
 
In this paper, a low-power DMF structure has been pro-
posed for direct sequence spread spectrum communication 
systems. The proposed DMF is based on a hybrid structure 
that employs the direct-form structure for local addition 
and the transposed-form structure for global addition to 
take advantages of both structures. The proposed structure 
leads to the reduction of switching memory elements by 
adopting register files. In addition, substantial number of 
computations is reduced by employing the differential co-
efficient scheme. Using the proposed hybrid structure, we 
achieved 46 % power reduction with 6 % area overhead, 
compared to the state-of-the-art low-power DMF. Further 
power reduction is expected by applying transistor-level 
circuit techniques to the adders and the register files. 
 
5. REFERENCES 
 
[1] R. L. Peterson, R. E. Ziemer, and D. E. Borth, Introduction to 
Spread Spectrum Communications. Englewood Cliffs, NJ: 
Prentice-Hall, 1995. 
[2] S. S. Rappaport and D. M. Grieco, “Spread spectrum signal 
acquisition: method and technology,” IEEE Commun. Mag., 
vol. 22, pp. 6-21, June 1984. 
[3] R. B. Ward and K. P. Yiu, “Acquisition of pseudo-noise signal 
by recursion aided sequential estimation,” IEEE Trans. Com-
mun., vol. 25, pp. 778-784, Aug. 1977. 
[4] G. L. Stuber, J. W. Mark, and I. F. Blake, “Sequential estima-
tion using bit estimation techniques,” Inform. Sci., vol. 32, pp. 
217-229, 1984. 
[5] M. D. Hahm, E. G. Friedman, and E. L. Titlebaum, “A com-
parison of analog and digital circuit implementations of low 
power matched filters for use in portable wireless communica-
tion terminals,” IEEE Trans. Circuits Syst. II, vol. 44, pp. 498-
506, June 1997. 
[6] K. Liu, W. Lin, and C. Wang, “A pipelined digital differential 
matched filter FPGA implementation & VLSI design,” in Proc. 
IEEE Custom Integrated Circuit Conf., 1996, pp. 75-78. 
[7] M. Liou and T. Chiueh, “A low-power digital matched filter 
for direct-sequence spread-spectrum signal acquisition,” IEEE 
J. Solid-State Circuits, vol. 31, pp. 933-943, June 2001. 
[8] S. Goto, T. Yamada, N. Takayama, Y. Matsushita, Y. Harada, 
and H. Yasuura, “A low-power digital matched filter for 
spread-spectrum systems,” in Proc. IEEE Int. Symp. Low 
Power Electronics and Design, 2002, pp. 301-306. 
[9] 0.25µm 2.5V CMOS Standard Cell Library Data Book. Sam-
sung Electronics Co., Ltd., 2000. 
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
4 bits
Register File
9 bits x 32
Register File
8 bits x 32
Register File
9 bits x 32 10
 b
its
Input
Output
11
 b
its
Sign extension /
Negation constant
8 (32/4) x 4 bits
32 x 4 bits
 
Figure 6. The proposed low-power hybrid digital matched filter (4 bits, 128-tap, 4× oversampling). 
Table 2.  Performance evaluation of the proposed hybrid low-power digital matched filter (4 bits, 128-tap, 4× oversampling). 
 Liou [7]† Goto [8]‡ Liu [6] Proposed 
Area 10623 gates 14372 gates 13624 gates 11261 gates 
# of Switching FFs 225 53 1306 79 
Power dissipation 0.908 mW/MHz 0.526 mW/MHz 3.384 mW/MHz 0.488 mW/MHz 
Direct-form Transposed-form Hybrid-form 
Register file Shift register Shift reg. + Reg. file
Prefilter Differential coefficient 
Architecture 
Characteristics 
Pipelined Adder Parallel Adder Carry-Select Adder Carry-Save Adder 
         †: 6-3 compressors are replaced by full adders.                 ‡: Threshold judgment is not considered for its loss of accuracy. 
II - 852
➡ ➠


Low-power hybrid structure of digital matched filters for direct sequence spread spectrum systems

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Low-power hybrid structure of digital matched filters for direct sequence spread spectrum systems

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