Abstract-We demonstrate the feasibility of using a CMOS laser driver for a low-power digital optical transmitter that is capable of at least 1-Gb/s operation. The transmitter employs low threshold lasers and zero-bias modulation. The circuit driver uses a strategy for low power consumption such that a majority of the total transmitter power is consumed by the laser instead of the electronics. The driver can function over a wide temperature range (77 K-300 K) for a variety of laser diodes

Fellow, IEEE Kam Y Lau

Melissa Y Li

Senior Member, IEEE Connie J Chang-Hasnain

Student Member, IEEE Leonard P Chen

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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 9, NO. 7, JULY 1997 997
A Low-Power 1-Gb/s CMOS Laser Driver for a
Zero-Bias Modulated Optical Transmitter
Leonard P. Chen,Student Member, IEEE, Melissa Y. Li, Connie J. Chang-Hasnain,Senior Member, IEEE,
and Kam Y. Lau,Fellow, IEEE
Abstract—We demonstrate the feasibility of using a CMOS
laser driver for a low-power digital optical transmitter that is
capable of at least 1-Gb/s operation. The transmitter employs
low threshold lasers and zero-bias modulation. The circuit driver
uses a strategy for low power consumption such that a majority
of the total transmitter power is consumed by the laser instead of
the electronics. The driver can function over a wide temperature
range (77 K–300 K) for a variety of laser diodes.
Index Terms— CMOS, cryogenic electronics, edge-emitting
lases, optical interconnections, semiconductor lasers, VCSEL’s,
zero-biased modulation.
I. INTRODUCTION
OPTICAL links are becoming more popular for short dis-tance data communications, such as parallel data trans-
mission using two-dimensional (2-D) vertical-cavity surface-
emitting laser (VCSEL) arrays and isolation of high-speed
cryogenic systems. In addition to high speeds and low bit-
error rates (BER), these systems require the link to have low
electrical power consumption, which conventional designs do
not emphasize.
We present a low power optical transmitter that uses zero-
bias modulation and a versatile CMOS laser driver. Zero-bias
modulation is attractive for its simplicity. Zero current is
supplied to the laser for a “0” b. For a “1” b, the laser is driven
by a current , which is greater than the threshold current
. DC biasing and feedback circuitry are eliminated with
this scheme. A disadvantage is that timing jitter occurs because
of a randomness in the turn-on delay of the laser. As a result,
the laser has to be driven with a larger peak current than for
threshold-bias modulation. However, for low bit rates (100’s
Mb/s), zero-bias modulation can be the low power solution
with only moderate power penalties for larger bit rates (1
Gb/s) [1].
Zero-bias modulation is especially suitable for low-
threshold lasers 1 mA) where the absolute drive current
is small ( 10 mA). This also allows us to take advantage of
Manuscript received January 28, 1997; revised March 25, 1997. This work
was supported by the Santa Barbara Research Center UC MICRO Program
under Grant 95-109. The work of L. Chen was supported by a Hughes
Fellowship.
L. P. Chen was with the Department of Electrical Engineering and Computer
Science, University of California at Berkeley, Berkeley, CA 94720-1772 USA.
He is now with the Santa Barbara Research Center, Goleta, CA 93117 USA.
M. Y. Li, C. J. Chang-Hasnain, and K. Y. Lau are with the Department
of Electrical Engineering and Computer Science, University of California at
Berkeley, Berkeley, CA 94720-1772 USA.
Publisher Item Identifier S 1041-1135(97)04930-6.
Fig. 1. Functional circuit diagram of the optical transmitter.
CMOS technology to design relatively low power optical
transmitters.
II. CIRCUIT DRIVER ARCHITECTURE
FOR ZERO-BIAS MODULATION
A laser diode is a current mode device. Therefore, an
efficient circuit driver should convert a digital input (usually
a voltage signal) to a train of current pulses. The functional
schematic shown in Fig. 1 is such a circuit driver implemented
in CMOS technology. It is similar to that used in conventional
GaAs and silicon bipolar driver circuits. A CMOS architecture
has the advantage of a wide temperature range where func-
tionality can be realized from normal room temperature to 77
K. Silicon bipolar transistors are not useful at 77 K because
their current gain collapses, whereas the mobility of CMOS
transistors increases.
In addition to the conventional differential pair, the driver
has a current mirror in the output stage. Low power operation
is achieved through the use of zero-bias modulation and
the additional current mirror. Bias-free modulation allows
the elimination of the laser’s dc-bias circuitry associated
with threshold-biasing. Moreover, there is no static power
consumption through the laser. The current mirror reduces
the static current (i.e., the tail current, of the differential
pair. In conventional designs, the laser is placed in an arm
of the differential pair. This implies that a static current of
would always have to flow. With the laser removed from
the differential pair, can be made a fraction of
1041–1135/97$10.00 1997 IEEE
998 IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 9, NO. 7, JULY 1997
Fig. 2. Comparison of the theoretical maximum bit rate that can be supported
by the circuit design given in the letter and a laser (for two threshold currents,
Ith). We used a link efficiency () of 0.15 and a laser carrier lifetime ( ) of
4 ns. At the receiver, noise on the “0” b (0) = 50-
 thermal noise, and
the “1” b (1) included shot noise and RIN, where RIN= =P 30 . P0 is the
optical power, and = 2.2 10 15 (mW)3. The laser curves are calculated
from (2) whereIm = nIt, andn = 10.
. In order to pulse the laser, the differential pair directs
through the mirror, which provides a current gain of.
Because is adjustable, the circuit is relatively robust
for differences in the laser’s turn-on voltage,
This architecture significantly reduces the average current
in the driver. The circuit consumes an average current of
in contrast to in the conventional scheme. It is assumed
that the data is not source coded, and there is an even
distribution of “0” and “1” b. An adjustable allows the
tuning of the minimum modulation current for a particular
bit rate, independent of the digital input signal level, and the
accommodation of different lasers’
III. D ESIGN CONSIDERATIONS
The driver’s power consumption is given by:
(1)
For a particular bit rate, low-power operation dictates that
and be minimized. is limited by
the laser’s and the headroom for the current source
connected to the laser.
We determine the as a function of bit rate required for
zero-bias modulation. The driving equation is the BER, and
from the noise probability densities associated with the digital
bits, we can express the BER as [1]:
BER (2)
is the bit rate; is the link efficiency; is the rms noise
current for the “0” (“1”) b at the receiver; and is the bit
shape at the receiver. We have used a simplified form of the
BER in (2) by assuming a worst case time delay, for
each “1” b, where and is the
laser’s carrier lifetime. Equation (2) is a valid approximation
for the and bit rates in which we are interested [1]. Fig. 2
shows the maximum bit rate (dashed curves) for a particular
, as predicted by (2), for typical laser parameters at 300 K
and a BER 10 . It is graphed versus , where /10.
We used a raised cosine function for .
Having determined the necessary , we can design the
driver for a minimum and by using the
circuit’s equations for bit rate and voltage headroom. We
associate with node 1 a time constant of
where is the small signal transconductance of and
is the total gate capacitance on node 1 (see Fig. 1). If
the bandwidth is notRC limited by the laser, the largest bit
rate the driver can support is estimated as :
Bit rate
(3)
where is the current mirror gain factor and
and are ’s mobility, oxide capacitance per
unit area, width, and length, respectively.
Because the lowest voltage at the input is assumed to be
the minimum is given by:
(4)
where is the drain-source saturation voltage of ,
and is the gate–source voltage of .
From (2), (3), and setting (4) to 3 V, we determined a set
of transistor sizes for a 1.2-m CMOS process, among which
6 m 1.2 m and 10. and are sized
such that there is sufficient gain for fast switching without
contributing too much parasitic capacitance at nodes 1 and
3. is used to pull node 1 to to provide a faster fall
time for the laser’s off condition. Fig. 2 shows the theoretical
maximum bit rate (solid curve) for our design at 300 K. This
is compared to the bit rate versus of a typical laser
(dashed curves). For bit rates below where the two curves
intersect, the circuit has sufficient drive current to modulate
the laser. For faster speeds, the circuit must operate at an
that is larger than required by the laser. The design can be
resized such that the lowest power consumption is realized for
the larger bit rates.
IV. EXPERIMENTAL RESULTS
We fabricated the driver through MOSIS using Orbit’s 1.2-
m CMOS process and hybridized it to a laser. The laser was
coupled through free space into a high speed photodetector.
was lowered until we measured a BER of 10while
keeping at approximately 3 V. Fig. 3 shows the
average power consumption for the transmitter using an edge-
emitting 1.3- m InGaAsP buried crescent laser provided by
Hughes Research Labs [3]. (See Table I) The entire transmitter
was cooled to 77 K where the laser’s 0.6 mA. The
laser consumed about 80% of the total power over the entire
frequency range. An eye diagram is also shown in Fig. 3 for
CHEN et al.: A LOW-POWER 1-Gb/s CMOS LASER DRIVER 999
Fig. 3. Experimental results for the transmitter’s power consumption using
the HRL laser at 77 K. (See Table I.)t is the minimum current for a BER
< 10 9 and a pseudorandom bit sequence of 223  1. The laser consumes
about 80% of the total power.VDD = 3.1 V, andVLaser = 2 V. The inset
shows an eye diagram for the transmitter at 1 Gb/s where the output was band
limited to 1.1 GHz. For this eye,It = 260A. At the right of the inset are
histograms for the “0” and “1” b distributions.
TABLE I
PARAMETERS FOR THE TWO LASERS THAT
WERE HYBRIDIZED TO THE DRIVER CIRCUIT
1-Gb/s operation at 77 K. A histogram of the bit distribution
is shown on the right indicating an error free zone.
An 850-nm VCSEL, which was fabricated in the Microlab
at the University of California at Berkeley, was also hybridized
to the driver and modulated bias-free at 300 K. (See Table I)
The largest possible bit rate we were able to modulate for a
BER 10 and a pseudorandom bit sequence of 21 was
about 200 Mb/s. For this setup, 3 V, 3.3 V,
350 A, and the average current through the laser was 1.2
mA for a total power consumption of 5 mW. We attribute the
bit-rate limitation principally to the high resistance at the laser
node (node 2 in Fig. 1). From the dc– curve, the laser has a
differential resistance of 512 at 1.1 mA, and the capacitance
of node 2 is estimated to be 1–2 pF [1/(5RC)195 Mb/s,
worst case]. Therefore, theRC limit at the laser node can pose
a fundamental limit to zero-bias modulation. A VCSEL with
a lower differential resistance and/or a smaller will help
to overcome this problem. Another solution would be to slew
node 2 with a larger current in order to improve the speed
performance. Of course, this does mean an increased penalty
in the total power consumption.
V. CONCLUSION
Low-power digital driver architectures other than the one
presented above can certainly be contrived. However, the
design shown in this paper offers a fundamental, yet extremely
versatile and flexible, low power circuit driver. First, because
is independent of the drive signal, the transmitter works
over a large digital input voltage range.
Second, the circuit is nonspecific toward a particular diode.
Due to the variable and , various types of lasers
with different (e.g., VCSEL’s or edge-emitters) and a wide
range of bit rates can be accommodated.
Third, the CMOS architecture allows functionality for a
large temperature range. We were able to demonstrate a
BER 10 at a bit rate of 1 Gb/s for an edge-emitter at 77
K and at a bit rate of 200 Mb/s for a VCSEL at 300 K. The
power consumption for these were 4.3 and 5 mW, respectively.
It must be noted that a bit rate of 200 Mb/s isnot an upper
bound for our laser driver at 300 K. The circuit is capable of
bit rates up to 1 Gb/s at room temperature for a large enough
tail current as shown in Fig. 2. In our case, we were limited by
the high resistance of the VCSEL coupled with the capacitance
at node 2. It is anticipated that 1 Gb/s operation at 300 K is
feasible with our driver hybridized to a submilliamp threshold
laser diode that exhibits a low differential resistance and/or a
low turn-on voltage. At 77 K, we were able to achieve a bit
rate of 1 Gb/s because the laser we used had a 1.1 V
and a differential resistance of 20 (see Table I).
Finally, this circuit driver is easily implemented as an output
buffer in any CMOS circuit where an optical interconnect is
being used to replace an electrical one.
ACKNOWLEDGMENT
The authors are grateful to W. Ng of HRL for the contri-
bution of the edge-emitting laser.
REFERENCES
[1] L. P. Chen and K. Y. Lau, “Regime where zero-bias is the low-power
solution for digitally modulated laser diodes”,IEEE Photon. Technol.
Lett., vol. 8, pp. 185–187, Feb. 1996.
[2] P. W. Shumate, “Lightwave Transmitters,”Optical Fiber Telecommuni-
cations II. Boston, MA: Academic, 1988, ch. 19, pp. 733–743.
[3] W. W. Ng, R. Craig, and H. W. Yen, “Dynamic characteristics of
high speedp-substrate GaInAsP buried crescent lasers,”J. Lightwave
Technol., vol. 7, pp. 560–567, 1989.


A Low-Power 1-Gb/s CMOS Laser Driver for a Zero-Bias Modulated Optical Transmitter

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A Low-Power 1-Gb/s CMOS Laser Driver for a Zero-Bias Modulated Optical Transmitter

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