Complementary metal-oxide-semiconductor (CMOS) technology is the dominant integrated circuit (IC) technology in modern electronics systems. As CMOS comprises of p-channel and n-channel transistors, there are parasitic PNPN paths that act as cross-coupled bipolar transistors capable of creating low-impedance paths between the power supply rails known as the “latchup” state. Latchup is destructive and requires a power cycle to restore operation. Latchup can be stimulated by ionizing radiation such as a high-energy proton or heavy-ions from deep space, resulting in a significant vulnerability in CMOS space systems. The sensitivity of an IC to single-event latchup (SEL) depends on various process parameters as well as design geometry. This work presents a method for the characterization of the geometric effects of CMOS layout on SEL. The dominant geometric contributors to the overall SEL sensitivity include: (1) substrate contact-to-source spacing (PWNS), (2) well contact-to-source spacing (NWPS), and (3) source-to-source spacing (SS)
