An Overview of Fully On-Chip Inductors

This paper focuses on full integration of passive devices, especially inductors with emphasis on multi-layer stacked (MLS) structures of fully integrated inductors using patterned ground shield (PGS) and fully integrated capacitor. Comparison of different structures is focused on the main electrical parameters of integrated inductors (e.g. inductance L, inductance density LA, quality factor Q, frequency of maximum quality factor F Qmax, self-resonant frequency FSR, and series resistance R DC ) and other non-electrical parameters (e.g. required area, manufacturing process, purpose, etc.) that are equally important during comparison of the structures. Categorization of inductor structures with most significant results that was reported in the last years is proposed according to manufacturing process. Final geometrical and electrical properties of the structure in great manner accounts to the fabrication process of integrated passive device. This work offers an overview and state-of-the-art of the integrated inductors as well as manufacturing processes used for their fabrication. Second purpose of this paper is insertion of the proposed structure from our previous work among the other results reported in the last 7 years. With the proposed solution, one can obtain the highest inductance density L A = 23.59 nH/mm 2 and second highest quality factor Q = 10.09 amongst similar solutions reported in standard technologies that is also suitable competition for integrated inductors manufactured in advanced technology nodes

A Silicon-Embedded Inductor Surrounded by Porous Silicon for Improved Quality Factor

International audienc

High-Q Backside Silicon-Embedded Inductor for Power Applications in μH and MHz Range

In this paper, a set of backside silicon-embedded inductors (BSEIs) is fabricated and characterized for potential applications in next-generation fully integrated power electronics. The fabrication technology of the BSEI is very similar to the through-silicon-via technology and has a high potential for post-CMOS integration. Without using magnetic material, an inductance as high as 13.8 mu H is achieved with an effective inductance density of 0.6 mu H/mm(2). For the 4.5 mm x 4.5 mm BSEIs with a high substrate resistivity, an inductance between 2 and 4 mu H, a dc resistance of 0.6-1.4 Omega, and a peak quality factor ranging from 18 to 23 occurring at 2-5 MHz are experimentally demonstrated. The effects of various physical design parameters are also experimentally studied, including coil outer dimension, metal width/spacing/ pitch, coil shape, and silicon resistivity. These measurement results illustrate the design flexibility of the proposed BSEI technology to allow tradeoffs of key electrical properties for meeting different requirements of various integrated power electronics