A design methodology to enable sampling PLLs to synthesise fractional-N frequencies

A novel design methodology is proposed to enable sampling phase-locked loops (SPLL) to synthesise fractional-N frequencies. To date, SPLL can only generate integer-N frequencies. The benefit is that the proposed SPLL has the advantages of both fractional-N phase-locked loop (FN-PLL) and SPLL, such as the faster frequency switching, a smaller phase jump and a larger loop gain. Since the frequency divider can be omitted in SPLL, the associated phase noise, power and hardware consumption can be ignored. Also, the design work is simplified, since the complex multi-phase frequency divider is not needed in the proposed fractional-N sampling phase-locked loop (FN-SPLL)

Double reference pulsed phase locked loop

A double reference pulse phase locked loop is described which measures the phase shift between tone burst signals initially derived from the same periodic signal source (voltage controlled oscillator) and delayed by different amounts because of two different paths. A first path is from the transducer to the surface of a sample and back. A second path is from the transducer to the opposite surface and back. A first pulse phase locked loop including a phase detector and a phase shifter forces the tone burst signal delayed by the second path in phase quadrature with the periodic signal source. A second pulse phase locked loop including a second phase detector forces the tone burst signals delayed by the first path into phase quadrature with the phase shifted periodic signal source

Improved phase locked loop receiver

Improved phase locked loop receiver tracks and demodulates a signal whose signal-to-noise ratio may be low and whose information sidebands are close in frequency. This receiver recovers the carrier from input signals and applies it to a demodulator which recovers the sidebands

Linear phase demodulator including a phase locked loop with auxiliary feedback loop

A phase modulated wave that may have no carrier power is demodulated by a phase locked loop including a phase detector for deriving an A.C. data output signal having a magnitude and a phase indicative of the phase of the modulated wave. A feedback loop responsive to the data output signal restores power to the carrier frequency component to the loop. In one embodiment, the feedback loop includes a phase modulator responsive to the phase modulated wave and the data output signal. In a second embodiment, carrier frequency power is restored by differentiating the data output signal and supplying the differentiated signal to an input of a voltage controlled oscillator included in the phase locked loop

Phase demodulation system with two phase locked loops Patent

Development of phase demodulation system with two phase locked loop

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

Wideband phase-locked angular modulator

A phase-locked loop (PLL) angular modulator scheme has been proposed which has the characteristics of wideband modulation frequency response. The modulator design is independent of the PLL closed-loop transfer function H(s), thereby allowing independent optimization of the loop's parameters as well as the modulator's parameters. A phase modulator implementing the proposed scheme was built to phase modulate a low-noise phase-locked signal source at the output frequency of 2290 MHz. The measurement results validated the analysis by demonstrating that the resulting baseband modulation bandwidth exceeded that of the phase-locked loop by over an order of magnitude. However, it is expected to be able to achieve much wider response still

Pulsed phase locked loop strain monitor

The RF output of a voltage controlled oscillator (VCO) is periodically gated to a transducer which produces acoustic waves in a bolt. The reflected acoustic waves are converted to electrical signals by the transducer and gated to a mixer which also receives the output from the VCO and produces an output which is filtered by a low pass filter. The output of filter is a dc signal proportional to the phase difference change from a fixed phase difference between the two input signals to the mixer. This dc signal is sampled at an instant and held by circuit in response to the "P" signal. The output of the circuit is integrated and then applied to the VCO to change the frequency of the VCO such that the phase difference between the two inputs to the mixer remains at the fixed phase difference. The frequency of the VCO is a measure of the change in strain of the bolt