6,436,424 research outputs found

    Performance management at design actvity level

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    The overriding aim of much of the engineering design research is to improve the performance of the design process, and consequently the product development process. Much has been written within the product development literature on the performance of the product development process. This work has been largely focused on the analysis of performance at the project or program level. The ability to relate the different research and draw generic lessons from the results has been stifled by the lack of consistency on the meaning of performance both at a generic level [2] and more specifically in design/development [3]. For example, although product and process performance have been distinguished within existing work we are unclear on how these relate or may be managed effectively. This paper begins with a brief review of research in the area of performance, with particular emphasis on design/product development, highlighting the main weaknesses in work to date. A fundamental and generic model of performance, related to knowledge based activities in design, is then presented. The model describes performance in terms of its key elements, efficiency and effectiveness, and provides a basis for modelling performance across different process levels, i.e. project, program, etc

    Outsourcing and Firm-level Performance

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    Using firm-level panel data from the German cost structure survey over the period 1992 to 2000, our empirical analysis shows that firms that increased material inputs relative to internal labor costs performed better in terms of gross operating surplus than other firms. However, firms that increased external services relative to internal labor costs, thus outsourcing service functions previously provided within the firm, performed worse. In sum, our findings support the view that firms tend to overestimate the benefits accruing from outsourcing of services previously provided internally.outsourcing, firm performance, business service sector

    GCE A level performance descriptions for accounting

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    Performance evaluation of SiC MOSFET in 5-level single phase converter

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    The use of silicon carbide (SiC) semiconductor power devices has been studied and evaluated in a wide variety of converters. The work presented in this paper shows the performance of C2M SiC MOSFETs compared to Si devices operating as switching elements in a 5-level, single phase, multilevel converter. The paper describes the multilevel converter platform used to undertake the evaluation study and experimental results for the operating temperature of the MOSFETs, and conversion efficiency are shown for frequencies ranging from 20 kHz to 80 kHz. Finally, a discussion of the results obtained to highlight the differences in the performance of the Si and SiC devices and the feasibility of using SiC in MLC

    Performance monitoring at the task and the response level

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    How errors and confl ict are processed in the human brain, has been extensively investigated over the last decades. In this review, we argue that error research has mainly focused on one type of errors, namely errors at the response level. Furthermore, research on conflict and errors has primarily used a very restricted set of experimental paradigms, raising the question as to whether the results from this research can be generalized to other forms of errors and confl ict. We thus argue to approach errors and confl ict from a broader perspective

    Hierarchical Beamforming: Resource Allocation, Fairness and Flow Level Performance

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    We consider hierarchical beamforming in wireless networks. For a given population of flows, we propose computationally efficient algorithms for fair rate allocation including proportional fairness and max-min fairness. We next propose closed-form formulas for flow level performance, for both elastic (with either proportional fairness and max-min fairness) and streaming traffic. We further assess the performance of hierarchical beamforming using numerical experiments. Since the proposed solutions have low complexity compared to conventional beamforming, our work suggests that hierarchical beamforming is a promising candidate for the implementation of beamforming in future cellular networks.Comment: 34 page

    Transformations of High-Level Synthesis Codes for High-Performance Computing

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    Specialized hardware architectures promise a major step in performance and energy efficiency over the traditional load/store devices currently employed in large scale computing systems. The adoption of high-level synthesis (HLS) from languages such as C/C++ and OpenCL has greatly increased programmer productivity when designing for such platforms. While this has enabled a wider audience to target specialized hardware, the optimization principles known from traditional software design are no longer sufficient to implement high-performance codes. Fast and efficient codes for reconfigurable platforms are thus still challenging to design. To alleviate this, we present a set of optimizing transformations for HLS, targeting scalable and efficient architectures for high-performance computing (HPC) applications. Our work provides a toolbox for developers, where we systematically identify classes of transformations, the characteristics of their effect on the HLS code and the resulting hardware (e.g., increases data reuse or resource consumption), and the objectives that each transformation can target (e.g., resolve interface contention, or increase parallelism). We show how these can be used to efficiently exploit pipelining, on-chip distributed fast memory, and on-chip streaming dataflow, allowing for massively parallel architectures. To quantify the effect of our transformations, we use them to optimize a set of throughput-oriented FPGA kernels, demonstrating that our enhancements are sufficient to scale up parallelism within the hardware constraints. With the transformations covered, we hope to establish a common framework for performance engineers, compiler developers, and hardware developers, to tap into the performance potential offered by specialized hardware architectures using HLS
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