Metal oxide-graphene field-effect transistor: interface trap density extraction model

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current-gate voltage relationship Ids-Vgs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance-gate voltage Ctot-Vgs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model

Method and apparatus for measurement of trap density and energy distribution in dielectric films

Trap densities in dielectric films are determined by tunnel injection measurements when the film is incorporated in an insulated-gate field effect transistor. Under applied bias to the transistor gate, carriers (electrons or holes) tunnel into traps in the dielectric film. The resulting space charge tends to change channel conductance. By feeding back a signal from the source contact to the gate electrode, channel conductance is held constant, and by recording the gate voltage as a function of time, trap density can be determined as a function of distance from the dielectric-semiconductor interface. The process is repeated with the gate bias voltage at different levels in order to determine the energy distribution of traps as a function of distance from the interface

Interface trap generation by FN injection under dynamic oxide field stress

Interface trap generation under dynamic (bipolar and unipolar) and dc oxide field stress has been investigated with the charge pumping technique. It is observed that regardless of stress type, whether dc or dynamic (bipolar or unipolar), and the polarity of stress voltage, interface trap generation starts to occur at the voltage at which Fowler-Nordheim (FN) tunneling through the oxide starts to build up. For positive voltage, interface trap generation is attributed to the recombination of trapped holes with electrons and to the bond breaking by the hydrogen (H and H+) released during stressing. For negative voltage, in addition to these two mechanisms, the bond breaking by energetic electrons may also contribute to interface trap generation. The frequency dependence of interface trap generation is also investigated. Interface trap generation is independent of stressing frequency for unipolar stress but it shows a frequency dependence for bipolar stress. ©1998 IEEE.published_or_final_versio

Detection of a single-charge defect in a metal-oxide-semiconductor structure using vertically coupled Al and Si single-electron transistors

An Al-AlO_x-Al single-electron transistor (SET) acting as the gate of a narrow (~ 100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET) can induce a vertically aligned Si SET at the Si/SiO_2 interface near the MOSFET channel conductance threshold. By using such a vertically coupled Al and Si SET system, we have detected a single-charge defect which is tunnel-coupled to the Si SET. By solving a simple electrostatic model, the fractions of each coupling capacitance associated with the defect are extracted. The results reveal that the defect is not a large puddle or metal island, but its size is rather small, corresponding to a sphere with a radius less than 1 nm. The small size of the defect suggests it is most likely a single-charge trap at the Si/SiO_2 interface. Based on the ratios of the coupling capacitances, the interface trap is estimated to be about 20 nm away from the Si SET.Comment: 5 pages and 5 figure

Selective Passivation of GeO2/Ge Interface Defects in Atomic Layer Deposited High-k MOS Structures.

Effective passivation of interface defects in high-k metal oxide/Ge gate stacks is a longstanding goal of research on germanium metal-oxide-semiconductor devices. In this paper, we use photoelectron spectroscopy to probe the formation of a GeO2 interface layer between an atomic layer deposited Al2O3 gate dielectric and a Ge(100) substrate during forming gas anneal (FGA). Capacitance- and conductance-voltage data were used to extract the interface trap density energy distribution. These results show selective passivation of interface traps with energies in the top half of the Ge band gap under annealing conditions that produce GeO2 interface layer growth. First-principles modeling of Ge/GeO2 and Ge/GeO/GeO2 structures and calculations of the resulting partial density of states (PDOS) are in good agreement with the experiment results

Comparison of near-interface traps in Al2_2O3_3/4H-SiC and Al2_2O3_3/SiO2_2/4H-SiC structures

Aluminum oxide (Al2O3) has been grown by atomic layer deposition on n-type 4H-SiC with and without a thin silicon dioxide (SiO2) intermediate layer. By means of Capacitance Voltage and Thermal Dielectric Relaxation Current measurements, the interface properties have been investigated. Whereas for the samples with an interfacial SiO2 layer the highest near-interface trap density is found at 0.3 eV below the conduction band edge, Ec, the samples with only the Al2O3 dielectric exhibit a nearly trap free region close to Ec. For the Al2O3/SiC interface, the highest trap density appears between 0.4 to 0.6 eV below Ec. The results indicate the possibility for SiC-based MOSFETs with Al2O3 as the gate dielectric layer in future high performance devices.Comment: 3 figures. Applied Physics Letters, accepted for publicatio

Correlation between most 1/f noise and CCD transfer inefficiency

The 1/f noise in MOS transistors has been investigated and is shown to correlate with charge transfer inefficiency experiments on surface-channel CCDs. Both independent phenomena can be quantitatively explained by the same interface state model. The oxide trap density turns out to vary by more than a factor 10. The 1/f noise is compared with McWhorter's number fluctuation model and with the mobility fluctuation model. The oxide trap density is calculated from the charge transfer inefficiency in surface CCDs. Both the quantitative agreement between oxide trap density and 1/f noise and the observed dependence of 1/f noise on gate voltage here give strong arguments in favour of the McWhorter model. The investigated MOS transistors fall into a category that cannot be explained by the present mobility fluctuation model