Fixed-complexity quantum-assisted multi-user detection for CDMA and SDMA

In a system supporting numerous users the complexity of the optimal Maximum Likelihood Multi-User Detector (ML MUD) becomes excessive. Based on the superimposed constellations of K users, the ML MUD outputs the specific multilevel K-user symbol that minimizes the Euclidean distance with respect to the faded and noise-contaminated received multi-level symbol. Explicitly, the Euclidean distance is considered as the Cost Function (CF). In a system supporting K users employing M-ary modulation, the ML MUD uses MK CF evaluations (CFE) per time slot. In this contribution we propose an Early Stopping-aided Durr-Høyer algorithm-based Quantum-assisted MUD (ES-DHA QMUD) based on two techniques for achieving optimal ML detection at a low complexity. Our solution is also capable of flexibly adjusting the QMUD's performance and complexity trade-off, depending on the computing power available at the base station. We conclude by proposing a general design methodology for the ES-DHA QMUD in the context of both CDMA and SDMA systems

Simplified ordering for fixed-complexity sphere decoder

This paper proposes a simplified ordering algorithm for the fixed-complexity sphere decoder (FSD). The new algorithm is developed from the analysis of the ordering for FSD from a geometrical point of view. Computer simulation is used to assess the improvements in bit-error rate (BER) performances of MIMO systems using the FSD with the original and the simplified ordering. Simulation results show that the new ordering method can achieve nearly the same BER as the original ordering method but with much less complexity. Copyright © 2010 ACM.postprintThe 6th International Wireless Communications and Mobile Computing Conference (IWCMC 2010), Caen, France, 28 June-2 July 2010. In Proceedings of the 6th International Wireless Communications and Mobile Computing Conference, 2010, p. 804-80

A Novel VLSI Architecture of Fixed-complexity Sphere Decoder

Fixed-complexity Sphere Decoder (FSD) is a recently proposed technique for Multiple-Input Multiple-Output (MIMO) detection. It has several outstanding features such as constant throughput and large potential parallelism, which makes it suitable for efficient VLSI implementation. However, to our best knowledge, no VLSI implementation of FSD has been reported in the literature, although some FPGA prototypes of FSD with pipeline architecture have been developed. These solutions achieve very high throughput but at very high cost of hardware resources, making them impractical in real applications. In this paper, we present a novel four-nodes-per-cycle parallel architecture of FSD, with a breadth-first processing that allows for short critical path. The implementation achieves a throughput of 213.3 Mbps at 400 MHz clock frequency, at a cost of 0.18 mm2 Silicon area on 0.13{\mu}m CMOS technology. The proposed solution is much more economical compared with the existing FPGA implementations, and very suitable for practicl applications because of its balanced performance and hardware-complexity; moreover it has the flexibility to be expanded into an eight-nodes-per-cycle version in order to double the throughput.Comment: 8 pages, this paper has been accepted by the conference DSD 201