Efficient estimation of die-level process parameter variations via the EM-algorithm

A new approach for efficient estimation of die-level process parameter variations based on the expectation- maximization algorithm is proposed. To estimate the parameters and enhance diagnostic analysis, dedicated embedded sensors have been designed. Additionally, to guide the test with the information obtained through monitoring process variations, maximum-likelihood method and adjusted support vector machine classifier is employed. The information acquired is re-used and supplement the circuit calibration. The proposed estimation method is evaluated on a prototype ADC converter with dedicated sensors fabricated in standard single poly, five metal 0.09-mum CMOS

Analog circuit testing and test pattern generation

Test vectors for structural testing of an analog circuit are selected by first selecting an initial set of test input vectors for the analog circuit. A set of faults is selected, comprising faults that each correspond to a respective node in the analog circuit and corresponding fault voltage value for that node. A measure of overlap is computed between probability distributions of test output signal values for the analog circuit in response to the test input vectors in the presence and absence of each of the faults from said set of faults respectively, as a function of estimated statistical spread of component and/or process parameter values in the analog circuit.; Test input vectors are selected from the initial set of test input vectors for use in testing on the basis of whether the measure of overlap for at least one if the faults is below a threshold value in response to the selected test input vector under control of the test selection compute

IC Testing methods and apparatus

An integrated circuit comprises a device under test and embedded test circuitry. The embedded test circuitry comprises a plurality of process monitoring sensors (14), a threshold circuit (22) for comparing the sensor signals with a threshold window having an upper and a lower limit and a digital interface (17) for outputting the threshold circuit signal. The process monitoring sensors (14) comprise circuitry based on the circuit elements of the device under test. This arrangement enables monitoring of circuit element performance, such as transistor properties, using process monitoring sensors which are embedded with the device under test, so that the same process parameter variations apply to the sensors as to the device under test. The sensors preferably match the physical layout of the device under test

Analog IC having test arrangement and test method for such an IC

An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation

Analog IC having test arrangement and test method for such an IC

An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means.; Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation

Stochastic analysis of deep-submicrometer CMOS process for reliable circuits designs

A time-domain methodology for statistical simulation of nonlinear dynamic integrated circuits with arbitrary excitations is presented. The statistical behavior of the circuits is described as a set of stochastic differential equations rather than estimated by a population of realizations and Gaussian closure approximations are introduced to obtain a closed form of moment equations. Statistical simulation of specific circuits shows that the proposed numerical methods offer accurate and efficient solution of stochastic differentials for variability and noise analysis of integrated circuits