Process Parameters Optimization of 14 nm p-Type MOSFET using 2-D Analytical Modeling

Simulations of a computer-generated downscaled device at 14nm gate length of p-type MOSFET is conferred in this paper. The device is scaled down from a 32nm transistor which is from the former research. A combination of insulatorconductor that were used includes a high-k material and a metalgate where in this research, Hafnium Dioxide (HfO2) is used as high-k material and Tungsten Silicide (WSi2) is used as a metal gate. A 14nm p-type transistor was virtually fabricated usingATHENA module and characterized its performance evaluation using ATLAS module in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The scaled down device is then optimized through process parameter variability using Taguchi Method. The objective is to find the best combination of fabrication parameter in order to achieve the targeted value of threshold voltage (VTH) and leakage current (IOFF) that are predicted by International Technology Roadmap for Semiconductors (ITRS) 2013. The results show that the ideal value for VTH and IOFF are 0.248635±12.7% V and 5.26x10-12A/um respectively and the results were achieved according to the ITRS specification

Statistical Modelling of 14nm N-types MOSFET

This paper focuses on virtual modelling and optimization of 14nm n-types planar MOSFET. Here, high-k dielectric and metal gate were used where the high-k material is Hafnium Dioxide (HfO2) and the metal gate is Tungsten Silicide (WSi2). 36 simulations of Taguchi L9 Orthogonal Array method were applied in order to obtain the best parameter design for optimization of both performance parameters which are threshold voltage (VTH) and leakage current (IOFF). The simulation and fabrication for n-type transistor was conducted through Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS for its electrical characterization. For analyzation of the impact parameters on VTH and IOFF, two noise parameters and four process parameters value were varied. From the simulations, the results show the best value were well within ITRS prediction where VTH and IOFF are 0.236737 V and 6.995705 nA/um respectivel

Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively

Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively

Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively