A 6-10 bit Reconfigurable 20MS/s Digitally Enhanced Pipelined ADC for Multi-Standard Wireless Terminals

A 20MS/s pipelined ADC architecture can be reconfigured in 10 clock cycles to resolve 6, 8, 9 or 10 bits at maximum resolution. A 9.1bit ENOB and 74dB SFDR with a power consumption of only 8mW was achieved by using background digital calibration and op-amp sharing techniques. The test chip, containing two ADC for I and Q processing within a wireless receiver, has been realized in a 0.13mum pure CMOS technology and uses 3.2mm2 silicon are

65 nm CMOS SSB mixer for UWB synthesiser

The present work addresses the design of a 65 nm CMOS wide-band singlesideband mixer for UWB synthesiser. The circuit has been designed inductorless and with few capacitors, in order to save silicon area and, at the same time, to get a mixer independent of the adopted frequency plan and synthesiser architecture.Particular attention has been paid to reducing the spurs as much as possible. In order to address a realistic investigation, the design has accounted also for the corner cases and the possible impairments in the input signals. A comparison with the state-of-the-art of the SSB mixers shows the low power consumption of the present work