Optimization of Circuits for IBM's five-qubit Quantum Computers

IBM has made several quantum computers available to researchers around the world via cloud services. Two architectures with five qubits, one with 16, and one with 20 qubits are available to run experiments. The IBM architectures implement gates from the Clifford+T gate library. However, each architecture only implements a subset of the possible CNOT gates. In this paper, we show how Clifford+T circuits can efficiently be mapped into the two IBM quantum computers with 5 qubits. We further present an algorithm and a set of circuit identities that may be used to optimize the Clifford+T circuits in terms of gate count and number of levels. It is further shown that the optimized circuits can considerably reduce the gate count and number of levels and thus produce results with better fidelity

A heat quench algorithm for the minimization of multiple-valued programmable logic arrays

This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.Computer and Electrical Engineering Journal, Vol. 22, No. 2, 1996, pp. 103-107, 1996imulated annealing has been used extensively to solve combinatorial problems. Although it does not guarantee optimum results, results are often optimum or near optimum. The primary disadvantage is slow speed. It has been suggested [1] that quenching (rapid cooling) yields results that are far from optimum. We challenge this perception by showing a context in which quenching yields good solutions with good computation speeds. In this paper, we present an algorithm in which quenching is combined with rapid heating. We have successfully applied this algorithm to the multiple-valued logic minimization problem. Our results suggest that this algorithm holds promise for problems where moves exist that leave the cost of the current solution unchanged. Key words: Multiple-valued logic, logic minimization, simulated annealing, heat quench, heuristic

A minimization algorithm for non-concurrent PLA's

This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.International Journal of Electronics, Vol. 73, No. 6, Dec. 1992, pp. 1113-1119In the design of certain self-checking programmable logic arrays (PLAs), at most one line is activated in the AND plane, such as PLAs are termed non-concurrent. A heuristic algorithm for the minimization of non-concurrent PLAs is presented. It operates on two adjacent cubes, replacing them by one, two, and sometimes more than two cubes. The algorithm produces the best solutions known so far