An On-Chip Sensor for Time Domain Characterization of Electromagnetic Interferences

International audienceWith the growing concerns about susceptibility of integrated circuits to electromagnetic interferences, the need for accurate prediction tools and models to reduce risks of noncompliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation. This paper presents an on-chip noise sensor dedicated to the time-domain measurement of voltage fluctuations induced by interference coupling

A new approach to modelling the impact of EMI on MOSFET DC behavior

A simple analytical model to predict the DC MOSFET behavior under electromagnetic interference (EMI) is presented. The model is able to describe the MOSFET performance in the linear and saturation regions under EMI disturbance applied to the gate. The model consists of a unique simple equivalent circuit based on a voltage dependent current source and a reduced number of parameters which can accurately predict the drift on the drain current due to the EMI source. The analytical approach has been validated by means of electric simulation and mesaurement and can be easily introduced in circuit simulators. The proposed modeling technique combined with the nth-power law model of the MOSFET without EMI, significantyly improves its accuracy in comparison with the n-th power law directy applied to a MOSFET under EMI impact.Peer ReviewedPostprint (published version

On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations

page number: 12International audienceWith the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins

Characterization of the Evolution of IC Emissions after Accelerated Aging

9 pagesInternational audienceWith the evolving technological development of integrated circuits (ICs), ensuring electromagnetic compatibility (EMC) is becoming a serious challenge for electronic circuit and system manufacturers. Although electronic components must pass a set of EMC tests to ensure safe operations, the evolution over time of EMC is not characterized and cannot be accurately forecast. This paper presents an original study about the consequences of the aging of circuits on electromagnetic emission. Different types of standard applicative and accelerated-life tests are applied on a mixed power circuit dedicated to automotive applications. Its conducted emission is measured before and after these tests showing variations in EMC performances. Comparisons between each type of aging procedure show that the emission level of the circuit under test is affected differently

Caractérisation et optimisation de l’émission électromagnétique de systèmes sur puce

Avec l’évolution technologique vers les petites dimensions, l’intégration de fonctions toujours plus complexes, et l’augmentation des vitesses de fonctionnement, la compatibilité électromagnétique des composants devient une des préoccupations majeures des concepteurs de circuits intégrés. Notre mémoire décrit une méthodologie de caractérisation des émissions parasites dans les circuits CMOS submicronique, basée principalement sur la mesure et la simulation d’un véhicule de test, réalisé en technologie CMOS 0.18µm. Les premiers chapitres sont consacrés à l’étude de l’origine des émissions parasites, à l’évaluation des modèles d’émissions des circuits intégrés déjà existants, et à la mise en place d’une nouvelle méthode prédictive permettant d’estimer le niveau de bruit dès la conception du composant. Un modèle dédié pour les entrées / sorties est également présenté. Dans les chapitres 3 et 4, afin de valider notre démarche, nous modélisons un circuit intégré et comparons les résultats de ces simulations aux mesures. Enfin, la caractérisation de différents motifs du circuit nous sert à établir des règles de dessin et donner des recommandations pour réduire les émissions électromagnétiques de systèmes sur puce. - Following the scale down of the integrated circuit (IC) technology and the continuous shift toward very high frequencies, the electromagnetic compatibility problems at IC level have recently risen in importance and become a major preoccupation for the designers. They cause several parasitic effects which may jeopardize the behavior of the chip. Our study presents a methodology to establish a predicting electromagnetic emission model. At the beginning of this work, we describe the origin of parasitic emissions and evaluate the existing emission models of IC. Then, we propose a new predicting model. In chapters 3 and 4, we describe a dedicated test vehicle, designed in CMOS 0.18µm technology, which is used for validating this new approach. Chip measurements and simulation results, using the proposed model, are compared. This chip illustrates also the possibility to use a predicting model to forecast the impact of low emission design techniques on the parasitic emissions of system on chips. The last chapter gives some design guidelines to reduce the electromagnetic emissions of IC

Caractérisation et optimisation de l'émission électromagnétique de systèmes sur puce

TOULOUSE-INSA (315552106) / SudocSudocFranceF

Modeling Magnetic Near-Field Injection at Silicon Die Level

International audienceNear-field injection at silicon die level is a promising application for various area such as the analyses of integrated circuit (IC) susceptibility to electromagnetic interferences and security for cryptographic applications. This paper presents a first attempt to simulate the voltage induced on integrated circuit interconnects by a magnetic field probe. The validation of the simulation results is based on near-field injection performed on a test chip containing various types of interconnects and on-chip voltage sensors

Evaluation of the Near-Field Injection Method at Integrated Circuit Level

International audienceNear-field injection is a promising method in order to induce local faults in integrated circuits. This method can be used for various applications such as electromagnetic attacks on secured circuits or susceptibility investigations. This paper aims at evaluating the ability of near-field scan injection to induce local disturbances in integrated circuits. The study relies on measurements performed by on-chip voltage sensors, which provide an accurate method to characterize the induced voltage fluctuations

Construction and Evaluation of the Susceptibility Model of an Integrated Phase-Locked Loop

6 pagesInternational audienceDeveloping integrated circuit immunity models has become one of the major concerns of integrated circuits suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign process. This paper presents the development process of the susceptibility model an integrated phase-locked loop to harmonic disturbances up to 1 GHz. The model construction is based on basic circuit information and S parameter measurements. An evaluation of the model accuracy is ensured by the characterization of internal voltage fluctuations with an on-chip sensor

Prediction of Aging Impact on Electromagnetic Susceptibility of an Operational Amplifier

International audienceThis paper deals with the impact of aging on the electromagnetic susceptibility level of a CMOS operational amplifier (opamp). The aging impact can be modelled by the variation of several parameters of the MOSFET model, to predict the evolution of electromagnetic susceptibility (EMS) of the opamp block during the aging process. I. INTRODUCTION The increasing use of high speed and complex electronic systems makes the electromagnetic compatibility (EMC) an important issue for the electronic manufacturers [1]. Some experimental results show the significant reduced EMC evolution after aging stress [2]. Thus how to ensure EMC during the whole lifetime of IC products, which is called electromagnetic robustness (EMR), becomes a new study in the recent years. As presented in only few works, the simulation can be used to predict the long-term EMC behaviour. For example, in [3], the increase of the electromagnetic emission of a DC-DC converter after thermal stress is modeled, which is associated to the degradation of filtering passive devices. In [4], the simulation results confirm the evolution of the EMS of a phase-locked loop (PLL) before and after aging. The aging affects the threshold voltage and the mobility of the MOSFET of the PLL. However, in these case studies only two statuses (the device before and after a period of aging) are measured and simulated. Thus there is a lack of more precise insight about the evolution of the different phases during the whole aging time. As a common electronic block, the operational amplifier is very susceptible to the external electromagnetic interference (EMI). The coupling of EMI on opamp inputs and power supply leads to a distortion of the output voltage, especially the generation of a voltage offset on its output which is harmful and hard to remove [5], [6]. In this study, with the aging stress injected in several parts of the amplifier, a worse DC output offset value at several frequencies could be observed, that means the device becomes more susceptible to the EMI with the aging. So the prediction of EMS evolution becomes important to help the IC designers to prevent EMC failure during the ICs' lifetime