Bipolar Transistors with Self-Aligned Emitter-Base Metallization and Back-Wafer-Aligned Collector Contacts

Electrical Engineering, Mathematics and Computer Scienc

Design and Fabrication of a Multi-Functional Programmable Thermal Test Chip

This paper focuses on the design and fabrication of a new programmable thermal test chip as a flexible and cost-effective solution for simplification of characterization/prototyping of new packages. The cell-based design format makes the chip fit into any modular array configuration. One unit cell is as small as 4x4 mm2, including 6 individually programmable micro-heaters and 3 resistance temperature detectors (RTDs). All micro-heaters and sensors have 4-point Kelvin connections for improved measurement accuracy. The chip contains 2 metal layers: 100 nm thin-film Titanium to create micro-heaters and RTDs, and 2 μm Aluminum to add single bump measurement units and daisy chain connections. These structures facilitate bump reliability investigations during thermal/power cycling tests in flip-chip assembly technology. The calibration curves of RTDs show a sensitivity of 12 $\Omega$/K which is improved by 50 percent compared to the state-of-the-art TTC. The proposed design provides higher spatial resolution in thermal mapping by accommodating 3 RTDs per cell. The dense configuration of micro-heaters increases the uniformity of the power dissipation, which enhances the accuracy of thermal interface material (TIM) characterizations. The steady-state infrared (IR) thermography of a 20x20 mm2 TTC, including 150 active micro-heaters, verifies the promising uniformity of the heat profile over the chip surface.Accepted author manuscriptElectronic Components, Technology and Material

Characterization of waferstepper and process related front- to backwafer overlay errors in bulk micro machining using electrical overlay test structures

To validate the Front- To Backwafer Alignment (FTBA) calibration and to investigate process related overlay errors, electrical overlay test structures are used that requires FTBA [1]. Anisotropic KOH etch through the wafer is applied to transfer the backwafer pattern to the frontwafer. Consequently, the crystal orientation introduces an overlay shift. A double exposure method is presented to separate the process-induced shift from the FTBA shift. The process induced overlay shift can run up to 3µm, large compared to the expected FTBA error (around 0.1 µm). The measured overlay distribution is 0.45 µm (3 ?) this includes both waferstepper and process related overlay errors. The overlay distribution, corrected for waferstepper related overlay errors, like lens distortion, resembles the overlay distribution of the bulk micromachining (BMM) process; 0.26µm (3?). The procedures described in this work provide a quantitative method of describing the waferstepper and process related front to backwafer overlay errors.Delft Institute of Microelectronics and Submicron TechnologiesElectrical Engineering, Mathematics and Computer Scienc

Self-healing approach for enhanced reliability of light emitting diodes (poster abstract)

Delft University of Technolog

Monitoring the restoration of interfacial contact for self healing thermal interface materials for LED and microelectronic applications

While conventional self healing materials focus on the restoration of mechanical properties, newer generations of self healing materials focus on the restoration of other functional (i.e. non-mechanical) properties. Thermal conductivity is an example of an important functional property of a Thermal Interface Material (TIM) for LED’s and microelectronics devices. Current TIMs are optimized to provide thermal conductivity for as long a time as possible, yet these materials have no self healin potential and any crack formed will only lead to a decreased or lack of thermal conductivity and will dramatically reduce life time of the component. In order to get a better insight on how, as function of time, self-healing TIM systems are able to recover structural (cracks) and interfacial (delamination, adhesion) damages, we have developed a new specific technique to monitor local heat conduction. This technique probes very locally the heat transfer through the material to monitor changes related to heat conduction. If the material is damaged (cracked), the cracking or delamination will result in a thermal impedance restricting the thermal transfer. If the material is self healing, the local thermal conduction paths will be restored in time. In order to probe the thermal transfer for conventional and our new self healing TIM materials, a dedicated silicon chip containing an array of 49 diodes spaced uniformly over a 1 cm2 area has been fabricated. Using this device, it is possible to map with high spatial resolution the efficiency of the local thermal transfer and to relate it to the recovery of pre-imposed damage. Such experiments will yield unique local and temporal insight into cohesion and adhesion recovery of our self-healing polymeric systems.Aerospace Structures & MaterialsAerospace Engineerin

Wafer Scale Flexible Interconnect Transfer for Hetrogeneous Integration

A polymer-based wafer level integration technology suitable for miniaturized and multi-functional systems integration was developed and demonstrated in this work. Wafer scale flexible interconnects were firstly fabricated on one wafer, and then transferred to another wafer. Such transfer process involved wafer bonding and application of sacrificial materials. A sacrificial layer was firstly placed on the surface of the transfer wafer, and the sandwich interconnect structures were then manufactured on top of the sacrificial layer. With the help of the sacrificial layer, the flexible interconnects were transferred to another wafer through wafer bonding process. Contact resistance structures were fabricated with the help of wafer bonding process, connecting and aligning metal contact layer on device wafer and metal layer embedded in transferred flexible interconnects. Such transferred contact resistance was measured through designed testing structures as a demo for wafer level heterogeneous integration.Electronic Components, Technology and Material

3D Align overlay verification using glass wafers

In the MEMS world, increasing attention is being given to 3D devices requiring dual-sided processing. This requires lithography tools that are able to align a wafer to both its back side as front side. Overlay describes how well front and back side layers are positioned with respect to each other. Currently there is no simple and fast method to qualify the overlay. This paper covers a method of measuring the overlay between front- and back side patterns using a glass substrate. We describe the methods used, special process requirements and measurement data. The main advantages of the presented method are the simplicity of the concept and the need for only basic fab processing equipment. The substrate employed is re-usable and low cost. The results are as follows: 1. Glass wafers can be used to measure front to back side overlay. The accuracy of the proposed method is better than 100 nm (3?) on ASML PAS 5000/5200 machines. On ASML PAS 5500 steppers, the expected accuracy is better than 80 nm (3?). 2. The proposed method of measuring the absolute glass shift, from a glass-on-silicon stack, yields unreliable information. This is due to deformation of the glass. An alternative method is described which builds on result 1 (above). 3. Processing of glass wafers has been established, and a glass overlay measurement wafer has been defined. 4. The benefit of Anti Reflective (AR) coatings is suspected, but not yet proven. Minimizing bi-refringency does not play a role in the measurement accuracy of glass wafers for overlay measurements.Delft Institute of Micro Electronics and Submicron TechnologyElectrical Engineering, Mathematics and Computer Scienc

A Wafer-Scale Process for the Monolithic Integration of CVD Graphene and CMOS Logic for Smart MEMS/NEMS Sensors

In this paper we present, for the first time, the successful monolithic wafer-scale integration of CVD graphene with CMOS logic for highly miniaturized smart sensing structures with on-chip readout electronics. The use of a patterned CMOS compatible catalyst for pre-defined regions of CVD graphene growth, and the transfer-free process used, allows the direct implementation of patterned graphene structures between the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. No significant deterioration of the graphene properties and of the CMOS logic gate performance due to the high temperature graphene growth step was observed. This is a significant leap towards industrial production of graphene-based smart MEMS/NEMS sensors.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic Components, Technology and Material