Physical IC debug ─ backside approach and nanoscale challenge

Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50–100 µm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique valid for nano technology ICs, is also presented that is based upon the formation of local trenches using the bottom of Shallow Trench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As a derivative from this process, a locally ultra thin silicon device can be processed, creating a back surface as work bench for breakthrough applications of nanoscale analysis techniques to a fully functional circuit through chip backside. Several applications demonstrate the power and potential of this new approach

No Place to Hide: Contactless Probing of Secret Data on FPGAs

Field Programmable Gate Arrays (FPGAs) have been the target of different physical attacks in recent years. Many different countermeasures have already been integrated into these devices to mitigate the existing vulnerabilities. However, there has not been enough attention paid to semi-invasive attacks from the IC backside due to the following reasons. First, the conventional semi-invasive attacks from the IC backside --- such as laser fault injection and photonic emission analysis --- cannot be scaled down without further effort to the very latest nanoscale technologies of modern FPGAs and programmable SoCs. Second, the more advanced solutions for secure storage, such as controlled Physically Unclonable Functions (PUFs), make the conventional memory-readout techniques almost impossible. In this paper, however, novel approaches have been explored: Attacks based on Laser Voltage Probing (LVP) and its derivatives, as commonly used in Integrated Circuit (IC) debug for nanoscale low voltage technologies, are successfully launched against a $60$ nanometer technology FPGA. We discuss how these attacks can be used to break modern bitstream encryption implementations. Our attacks were carried out on a Proof-of-Concept PUF-based key generation implementation. To the best of our knowledge this is the first time that LVP is used to perform an attack on secure ICs