Design of a high speed and power efficient quarter-rate clock and data recovery circuit

Due to the advantage in technology and multi-media, the demand for data communication has increased tremendously. More standards for high speed low power communication have been established, i.e. Serial Advanced-Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB) and etc. In the receiver design, the clock and data recovery (CDR) circuit is an important block as the clock signal is embedded in the receiving data. This thesis presents several new circuit designs to improve the performance of the CDR circuit. First, a new quarter-rate linear phase detector (PD) is proposed to reduce the circuit complexity of the reported quarter-rate linear PD design. Besides that, the proposed PD applies UP pulse-widening technique to resolve the issue of small UP pulses. The existing PDs with UP pulse-widening techniques have more output signals, which increases the difficulties in designing the Charge Pump (CP). In the proposed PD, the number of output signals has been successfully minimized. This thesis also provides propagation delay analysis of the proposed PD. A set of equations is derived from the analysis to predict the characteristic curve of the proposed PD. At the linear region, the accuracy of the prediction results is 98% of the simulation results. The effect on propagation delay at various phase differences is also being discussed.DOCTOR OF PHILOSOPHY (EEE

A low power wideband differential transimpedance amplifier for optical receivers in 0.18-μm CMOS

This paper presents a low power wideband differential TIA for optical receivers. The wideband operation is achieved by modifying a conventional regulated cascode input stage and combining it with a feedback amplifier in a 0.18μm CMOS process. The post-layout simulation results show that the proposed TIA has a bandwidth of 4.5 GHz, average input referred noise current spectral density of 13.7 pA/sqrtHz from DC to 7 GHz, and transimpedance gain of 64.8 dBO. The proposed TIA dissipates only 3.5 mW with a 1.8 V power supply. The core circuit occupies a chip area of 97 μm × 53 μm

A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector

This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18- μm CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply

Integrated circuits design for neural recording sensor interface

Neural signal recording is attracting more and more attention, as it provides an necessary approach to read brain activities, understand the brain operation and restore the lost motor function of the body. One of the most important modules in the neural recording system is the sensor interface IC, which captures, amplifies, filters, and digitizes the weak neural signal. In order to preserve free movement of the subject under testing and minimize the risk of infection, the sensor interface IC is usually implanted under the skin or skull with wireless transmission. The nature of the neural signal and its recording scenarios impose rigid design specifications to the sensor interface IC, such as low noise, low power, low cut-off frequency and minimum chip size. Many designs have been reported recently to tackle these challenges in neural recording system. In this paper, design techniques for neural recording sensor interface IC will be introduced, including the design of system architecture and neural amplifier. Methods to realize low power, low noise and low cut-off frequency are investigated. In addition, the methods to achieve system power and area optimization are also discussed.Accepted versio

Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit

In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm will leads to a longer lock time for phase tracking loop and small ppm will leads to more switching time between the loops. A novel lock detector with hysteresis property is proposed in this paper. It provides two different ppms in both different conditions; a smaller ppm for in-lock condition and a larger ppm for out-of-lock condition. This paper also provides a detailed analysis of the proposed lock detector at different conditions. The proposed lock detector is simulated in 0.18- um technology and it consumes 1.1-mW at a 1.8V supply voltage.Accepted versio

Low power implantable neural recording front-end

Low power smart electronic designs for neural recording applications have recently become a major research topic in circuits and system society. Challenged by the complicated nature of the biology-electronic interface, implantable neural recording circuits must offer high quality signal acquisition while consuming as little power as possible. Furthermore, many applications demand on-chip smart features to maximize energy efficiency as well as to assist the subsequent software-based digital signal processing. This paper reviews the recent advancements in the field, followed by a proposed ultra low-power recording front-end. The proposed design consists of an adjustable gain and bandwidth low-noise amplifier, a bandpass filter, a unity gain buffer and a 9-bit ADC. When simulated using a 0.18 μm/1 V CMOS process, the whole channel consumes only 2.76 μW

A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems

This paper presents an ultra low-power SAR ADC in 0.18 μm CMOS technology for epileptic seizure detection applications. The ADC is powered by a single supply voltage of both analog and digital circuits to avoid using the level-shifters. A latched comparator is used to quickly generate the comparison results while consuming no DC current. Split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. A smaller-than-unit capacitor is used at the end of the least significant bit array to mitigate the negative impact of the parasitic components on the linearity of the capacitors array. As a result, both DNL/INL and SNDR of the ADC is improved. Our post-layout simulation shows that at 1 V supply, 1 kS/s the proposed SAR archives 8.7 ENOB while consuming only 9.87 nW. This yields an FOM of 23.7 fJ/conversion-step. Its leakage power consumption is 1.46 nW

A current-mode stimulator circuit with two-step charge balancing background calibration

Current-mode CMOS stimulation systems have offered unprecedented opportunities for accurate and high through put in-vitro and in-vivo physiological studies. As these circuits are in long term contact with living organisms, they must be flexible, safe and power efficient. Any mismatch in biphasic current pulses will result in charge imbalance, leading to tissue/cell damage. Therefore, it is the most important to maintain the balance of the charge injected and retracted by the anode and the cathode, respectively. This work first adjusts the body biasing voltage of the anode to match with the cathode current. It is robust, process-variation-aware and can reduce the imbalanced current to less than 1%. Second, any residue charge at the stimulation site is retracted only when it reaches a critical value. This process is performed in the background and thus does not disturb the front-end operation. Overall, it can achieve less than 0.4 nA DC error current and thus is a suitable candidate for long term stimulation applications

A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications

This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW