Real-time digital video multiplexer synchronisation implementation with CPLD

This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.---- Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.Many video applications in security areas such as close circuit television (CCTV) require multiple video channels which must be multiplexed into a single video streanm. The industry can only afford to have a few frames or fields per camera. This paper emphasises on a novel hardware design using an algorithm for synchronising the analogue video inputs. Therefore the proposed multiplexer system is able to achieve a constant stream of 50 digital video fields per second using a CPLD (Complex Programmable Logic Device) for 625/50 video system

An Efficient Mode Decision Algorithm Based on Dynamic Grouping and Adaptive Adjustment for H.264/AVC

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”The rate distortion optimization (RDO) enabled mode decision (MD) is one of the most important techniques introduced by H.264/AVC. By adopting the exhaustive calculation of rate distortion, the optimal MD enhances the video encoding quality. However, the computational complexity is significantly increased, which is a key challenge for real-time and low power consumption applications. This paper presents a new fast MD algorithm for highly efficient H.264/AVC encoder. The proposed algorithm employs a dynamic group of candidate inter/intra modes to reduce the computational cost. In order to minimize the performance loss incurred by improper mode selection for the previously encoded frames, an adaptive adjustment scheme based on the undulation of bitrate and PSNR is suggested. Experimental results show that the proposed algorithm reduces the encoding time by 35% on average, and the loss of PSNR is usually limited in 0.1 dB with less than 1% increase of bitrate

An efficient fast mode decision algorithm for H.264/AVC intra/inter predictions

H.264/AVC is the newest video coding standard, which outperforms the former standards in video coding efficiency in terms of improved video quality and decreased bitrate. Variable block size based mode decision (MD) with rate distortion optimization (RDO) is one of the most impressive new techniques employed in H.264/AVC. However, the improvement on performance is achieved at the expense of significantly increased computational complexity, which is a key challenge for real-time applications. An efficient fast mode decision algorithm is then proposed in this paper. By exploiting the correlation between macroblocks and the statistical characteristics of sub-macroblock in MD, the video encoding time can be reduced 52.19% on average. Furthermore, the motion speed based adjustment scheme was introduced to minimize the degradation of performanc

New line-interactive UPS system with DSP-based active power-line conditioning

This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.---- Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

A general framework for efficient FPGA implementation of matrix product

Original article can be found at: http://www.medjcn.com/ Copyright Softmotor LimitedHigh performance systems are required by the developers for fast processing of computationally intensive applications. Reconfigurable hardware devices in the form of Filed-Programmable Gate Arrays (FPGAs) have been proposed as viable system building blocks in the construction of high performance systems at an economical price. Given the importance and the use of matrix algorithms in scientific computing applications, they seem ideal candidates to harness and exploit the advantages offered by FPGAs. In this paper, a system for matrix algorithm cores generation is described. The system provides a catalog of efficient user-customizable cores, designed for FPGA implementation, ranging in three different matrix algorithm categories: (i) matrix operations, (ii) matrix transforms and (iii) matrix decomposition. The generated core can be either a general purpose or a specific application core. The methodology used in the design and implementation of two specific image processing application cores is presented. The first core is a fully pipelined matrix multiplier for colour space conversion based on distributed arithmetic principles while the second one is a parallel floating-point matrix multiplier designed for 3D affine transformations.Peer reviewe

Improved multimedia server I/O subsystems

This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.---- Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.The main function of a continuous media server is to concurrently stream data from storage to multiple clients over a network. The resulting streams will congest the host CPU bus, reducing access to the system's main memory, which degrades CPU performance. The purpose of this paper is to investigate ways of improving I/O subsystems of continuous media sewers. Several improved I/O subsystem architectures are presented and their performances evaluated. The proposed architectures use an existing device, namely the Intel i960RP processor. The objective of using an I/O processor is to move the stream and its control from the host processor and the main memory. The ultimate aim is to identify the requirements for an integrated I/O subsystem for a high performance scalable media-on-demand server

Floating-Point Matrix Product on FPGA

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Reproductive biology of hilsa shad (Tenualosa ilisha) in coastal waters of the northwest of Persian Gulf

Some aspects of the reproductive biology of Hilsa Shad, Tenualosa ilisha from the Persian Gulf and rivers of Khouzestan Province of Iran were analyzed. A total of 485 fish were sampled by gillnet from landing center of Arvand (AR) and Bahmanshir (BR) rivers during period of April 2010 to September 2010. Reproductive characteristic of T. ilisha showed that sex ratio is M:F=1:2, in PG, AR and BR. This means that females predominate than males. Monthly variations in Gonadosomatic Index (GSI) of both sexes were quite apparent. In PG, maximum values were recorded in April for male and female. In AR and BR, maximum values were recorded in June and May for male and female, respectively. Changes in GSI indices are considered as a proof that maturation season in AR and BR is started from March and spawning is started from April to July in AR and BR is started from March to August. The Length - Weight relationship was measured for PG as W= 1.459L^2.687, AR and BR as W=2.189L^3.166 and W=1.840L^2.937, respectively