16 research outputs found

    ATLAS detector and physics performance: Technical Design Report, 1

    Get PDF

    Prospects of FPGAs for the ATLAS LVL2 Trigger

    No full text
    This note intends to give an overview over the possible evolution of FPGAs, new developments in the field of reconfigurable hardware, the development of hardware programming schemes, and, last but not least, the practical applications of reconfigurable computing in general and for the LVL2 trigger. The main areas in the LVL2 trigger, where FPGAs could advantageously be used, are the ROB complex and an acceleration of time-critical pattern recognition algorithms

    Pattern recognition algorithms on FPGAs and CPUs for the ATLAS LVL2 trigger

    No full text
    Recent studies of the level-two (LVL2) trigger of the ATLAS detector show that it will be possible to run the trigger algorithms at high luminosity with a reasonable number of general-purpose processors, using a sequential selection scheme and guidance from the Region-of- Interest (RoI) provided by the LVL1 trigger. The computing power requirements for B-physics, which is studied at low luminosity, are much greater than those at high luminosity as there is no LVL1- guidance for the track finding algorithms. Instead, track finding is performed for the entire Inner Detector volume. Currently, 2500 commodity CPUs would be required to supply the necessary computing power for the B-physics trigger. We describe a system of only 200 computing nodes which would be capable of performing the B-physics triggering. Each of these nodes is made up of a commodity PC and a FPGA co-processor board. Each node processes an entire event. The different tasks are allocated to the appropriate hardware device (CPU or FPGA). Track reconstruction requires a variety of different steps, some of which are suited to parallel processing, whereas others require sequential execution. For some tasks, floating-point arithmetic is needed. The flexibility of the PC/FPGA combination meets these varied requirements well. (10 refs)

    ATLANTIS - a modular, hybrid FPGA/CPU processor for the ATLAS

    No full text
    ATLANTIS realizes a hybrid architecture comprising an industry standard PC platform plus different FPGA based modules for high-performance I/O (AIB) and computing (ACB). It is a flexible and modular system which can be the platform for several applications. CompactPCI provides the basic communicationmechanism, enhanced byaprivate bus. The system can be tailored to a wide range of applications by selecting an appropriate combination of modules. Acceleration of computing intensiveAtlas level-2-trigger tasks has been demonstrated with an ACB based system. The Atlas RoD and RoB systems will profit from the flexible and highly efficientAIBI/Oarchitecture. Various highspeed interface modules (e.g., S-Link / M-Link) are supported, allowing up to 28 links per CompactPCI crate
    corecore