Hot Carrier Injection Effects in the Ultrashallow Body SONOS Gate Power MOSFET

In this paper, threshold voltage (VTH) stability of the ultrashallow body silicon-oxide-nitride-oxide-silicon gate power MOSFET (SG-MOSFET) under hot carrier injection conditions is characterized and discussed. Experimental results indicate that hot electron injection will increase the VTH from 1 to 2 V in the lifetime of the device. On the other hand, hot hole injection has no significant influence on the VTH stability of the device. The different effects caused by hot electron injection and hot hole injection are explained by using numerical analysis and experimental characterization, and results suggest that the VTH stability of the ultrashallow body SG-MOSFET will be improved if the short channel effect of the structure can be suppressed

Planar SONOS Gate Power MOSFET with an Ultra-Shallow Body Region

In this paper, a planar silicon-oxide-nitride-oxide-silicon (SONOS) gate power MOSFET (SG-MOSFET) with a 0.3 mu m ultra-shallow heavily doped p-body region is presented. The ultra-shallow body provides a much reduced parasitic JFET resistance, resulting in a low specific on-resistance of 18 m Omega.mm(2) for a planar device. At the same time, no punch-through problem is caused by the ultra-shallow body, and the avalanche breakdown voltage of the device is 29.5 V. The product of the on-resistance and gate charge of the ultra-shallow body SG-MOSFET is 43 m Omega.nC at V-GS = 4.5 V. The non-optimized performance obtained for this structure is comparable to that of trench power MOSFETs fabricated using more advanced technologies

Charge-trapping characteristics of Ga2O3 nanocrystals for nonvolatile memory applications

The charge-trapping characteristics of Ga2O3 nanocrystals (NCs) with and without nitrogen incorporation were investigated based on Al/Al2O3/Ga2O3/SiO 2/Si capacitors. The formation of Ga2O3 NCs and their chemical bonding states were characterized by transmission electron microscopy and X-ray photoelectron spectroscopy. Compared with the device with Ga2O3 NCs as charge-trapping layer, the one with nitrided Ga2O3 NCs showed a larger memory window (4.7 V at ±10-V sweeping voltage), higher program speed (3.0 V at 100-μs +10 V), and data retention (charge loss of 27% at 125°C), due to higher charge-trapping efficiency of the nitrided Ga2O3 NCs and nitrogen-induced suppressed formation of interlayer at the Ga2O 3/SiO2 interface. © 2012 The Electrochemical Society

High-Q Backside Silicon-Embedded Inductor for Power Applications in μH and MHz Range

In this paper, a set of backside silicon-embedded inductors (BSEIs) is fabricated and characterized for potential applications in next-generation fully integrated power electronics. The fabrication technology of the BSEI is very similar to the through-silicon-via technology and has a high potential for post-CMOS integration. Without using magnetic material, an inductance as high as 13.8 mu H is achieved with an effective inductance density of 0.6 mu H/mm(2). For the 4.5 mm x 4.5 mm BSEIs with a high substrate resistivity, an inductance between 2 and 4 mu H, a dc resistance of 0.6-1.4 Omega, and a peak quality factor ranging from 18 to 23 occurring at 2-5 MHz are experimentally demonstrated. The effects of various physical design parameters are also experimentally studied, including coil outer dimension, metal width/spacing/ pitch, coil shape, and silicon resistivity. These measurement results illustrate the design flexibility of the proposed BSEI technology to allow tradeoffs of key electrical properties for meeting different requirements of various integrated power electronics

A novel integrated power inductor with vertical laminated core for improved L/R ratios

In this letter, a novel integrated power inductor with a vertical laminated NiFe magnetic core for improved inductance to resistance ratio (L/R) ratios is proposed and demonstrated. Both the windings and magnetic core are accommodated within a groove at the backside of a silicon substrate and connected to the front-side IC through vias for compactness. NiFe is used to increase the inductance, and vertical lamination is used to suppress the eddy current in the magnetic core and assist hard axis alignment. A 1-mm2 embedded inductor with 131-nH inductance and 60-mΩ dc resistance working in megahertz range is fabricated. The L/R ratio is increased by seven times compared with integrated inductors with similar area, making it suitable for portable electronics power conversion system-on-chip applications

A Novel Silicon-Embedded Toroidal Power Inductor With Magnetic Core

In this letter, a novel post-CMOS silicon-embedded toroidal power inductor with an MnZn ferrite composite core is proposed and demonstrated. The inductor is accommodated within the groove at the backside of a Si chip and connected to the front-side IC through vias for area saving, electromagnetic interference suppression, and large power-handling capability. A 2.9-mm(2) embedded inductor with an inductance of 43.6 nH and a peak Q-factor of 16.2 is fabricated. It achieves a saturation current of 10 A, making it promising for on-chip light-emitting diode driver applications

A New Embedded Inductor for ZVS DC-DC Converter Applications

In this paper, a new tapered silicon-embedded coreless power inductor is proposed and demonstrated. The width and depth for the different turns of the inductor are designed with different values to reduce the proximity effect. An 18.6 nH inductance and a peak Q factor of 12.1 are achieved at 23 MHz within a chip area of 0.8 mm(2). The AC power loss of the inductor is reduced by a maximum of 56% using the novel design. The inductor shows a peak efficiency of 91% in ZVS conversion applications, and is the highest in monolithic ZVS DC-DC converters reported so far

Integrated Power Devices and TCAD Simulation

From power electronics to power integrated circuits (PICs), smart power technologies, devices, and beyond, Integrated Power Devices and TCAD Simulation provides a complete picture of the power management and semiconductor industry. An essential reference for power device engineering students and professionals, the book not only describes the physics inside integrated power semiconductor devices such lateral double-diffused metal oxide semiconductor field-effect transistors (LDMOSFETs), lateral insulated-gate bipolar transistors (LIGBTs), and super junction LDMOSFETs but also delivers a simple introduction to power management systems. Instead of abstract theoretical treatments and daunting equations, the text uses technology computer-aided design (TCAD) simulation examples to explain the design of integrated power semiconductor devices. It also explores next generation power devices such as gallium nitride power high electron mobility transistors (GaN power HEMTs). Including a virtual process flow for smart PIC technology as well as a hard-to-find technology development organization chart, Integrated Power Devices and TCAD Simulation gives students and junior engineers a head start in the field of power semiconductor devices while helping to fill the gap between power device engineering and power management systems