An atomistic investigation of the impact of in-plane uniaxial stress during solid phase epitaxial regrowth

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Study of self-limiting oxidation of silicon nanoclusters by atomistic simulations

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Electrical pump & probe and injected carrier losses quantification in Er doped Si slot waveguides

Electrically driven Er3+ doped Si slot waveguides emitting at 1530 nm are demonstrated. Two different Er3+ doped active layers were fabricated in the slot region: a pure SiO2 and a Si-rich oxide. Pulsed polarization driving of the waveguides was used to characterize the time response of the electroluminescence (EL) and of the signal probe transmission in 1 mm long waveguides. Injected carrier absorption losses modulate the EL signal and, since the carrier lifetime is much smaller than that of Er3+ ions, a sharp EL peak was observed when the polarization was switched off. A time-resolved electrical pump & probe measurement in combination with lock-in amplifier techniques allowed to quantify the injected carrier absorption losses. We found an extinction ratio of 6 dB, passive propagation losses of about 4 dB/mm, and a spectral bandwidth > 25 nm at an effective d.c. power consumption of 120 μW. All these performances suggest the usage of these devices as electro-optical modulators

Influence of induced stress on enrichment kinetic during local Ge condensation of SiGe/SOI mesas

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Insights in accesses optimization for nFET low temperature Fully Depleted Silicon On Insulator devices

session Annealing Technology S2-07International audienceThis work gives insights on the performance levers to optimize nFET Fully Depleted Silicon On Insulator sheet resistance with low temperature activation. Optimum dopant concentration, i.e clusterization limit for arsenic and phosphorus activated at 600°C has been extracted. This study shows that phosphorus appears to be the best candidate for nFET low temperature doping. Solid Phase Epitaxial Regrowth at 600°C enables to reach activation levels identical to the thermodynamic equilibrium at 1050°

Echangeur compact performant nettoyable cote externe a serpentins integres: qualification thermique

SIGLECNRS RP 400 (1004) / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs

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Low temperature junction formation by solid phase epitaxy on thin film devices: Atomistic modeling and experimental achievements

session Novel Process and Devices S8-04International audienceIn this paper, we address the problem of junction formation with a low temperature processing (≤ 600°C) through Solid Phase Epitaxial Regrowth. We present the main experimental achievements and suggest solutions to optimize the junctions. In particular, atomistic simulations based on kinetic Monte Carlo (kMC) method allow getting insight into the complex physical phenomena that take place during junction formation

Implantation and epitaxial effects on strained-Silicon-on-Insulator transport Com. a 2006 European Materials Research Society Meeting, Symposium B ‘From Strained

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