VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm

As artificial neural networks continue to gain popularity in the domain of pattern recognition, there have been growing demands for these models to be executed at high-speeds. Thus, to cater to this need, the VLSI design and implementation of a neurohardware for high-speed pattern recognition is proposed in this research. The UTM-Neuroprocessor implements the Kohonen Neural Network for pattern classification. High-speed pattern classification by the neural paradigm is achieved through massively parallel execution based on the neuron-parallel processing approach. For proof of concept purposes, a 10x10 UTM-Neuroprocessor, which implements a 10x10 Kohonen network, was developed in this work. The design and rapid FPGA prototyping of the neuroprocessor was achieved using VHDL and the Altera Nios embedded system development kit. The FPGA-based prototype of the 10x10 UTM-Neuroprocessor is able to function at a frequency of 100 MHz and delivers performances up to 5.079 GCPS and 2.285 GCUPS. Software components, including a VB-based GUI, were also developed to allow execution of pattern recognition applications on the UTM-Neuroprocessor. For efficient VLSI implementation of the UTM-Neuroprocessor, the combined FPGA-VLSI approach was proposed. Correspondingly, the VLSI design of a 2x2 array computation engine, termed the Array_2x2 microchip, was developed in the AMI 0.5µm process technology and fabricated at the Europractice IC foundry. The fabricated Array_2x2 microchip can be applied to produce a 2x2 UTM-Neuroprocessor, in the combined FPGA-VLSI implementation approach. The design consumes an area of 16.9 mm2 on silicon and is encapsulated in 84-pin PGA package. SPICE simulations of the Array_2x2 design proved functionality at an operating frequency of 90 MHz. The microchip is able to deliver performances of up to 169.41 MCPS and 75.78 MCUPS MCUPS for a 2x2 UTM-Neuroprocesso

Die Design Of A Transmitting Transistor In A 175 MHz Power Amplifier At 28V

This paper presents the die design of a NPN transistor, which is targeted for operation in a power amplifier. The proposed die is designed using epitaxial planar bipolar junction technology. The transistor die is designed for operation in the 175MHz frequency range with a 28V biasing. It is capable of producing a maximum output power of 4W. It can be utilized in Class A, Class B or Class C power amplifiers meant for transmission purposes such as in mobile communication, industrial communication or military transmitters. The power amplifier is typically placed before the antenna in transmitter systems. It is best to couple the design in a two-stage amplifier to produce a significantly higher-powered signal for transmission

Asic design of a kohonen neural network microchip

This paper discusses the Kohonen neural network (KNN) processor and its KNN computation engine microchip. The ASIC design of the KNN processor adopts a novel implementation approach whereby the computation of the KNN algorithm is performed on the custom ASIC microchip and its operations are governed by a FPGA based controller. Thus, the ASIC implementation of the KNN processor is derived through integration between a custom ASIC and FPGA. The 3.3V AMI 0.5um CO5M-D process technology was used to achieve the VLSI design of the computation engine microchip and the entire design adopted the BBX cell based methodology, which is a viable alternative to conventional ASIC methodology

Very large scale integrated circuit (VLSI) of a neurohardware processor implementing the kohonen neural network algorithm

As artificial neural networks continue to gain popularity in the domain of pattern recognition, there have been growing demands for these models to be executed at high-speeds. Thus, to cater to this need, the VLSI design and implementation of a neurohardware for high-speed pattern recognition is proposed in this research. The UTM-Neuroprocessor implements the Kohonen Neural Network for pattern classification. High-speed pattern classification by the neural paradigm is achieved through massively parallel execution based on the neuron-parallel processing approach. For proof of concept purposes, a 10x10 UTM-Neuroprocessor, which implements a 10x10 Kohonen network, was developed in this work. The design and rapid FPGA prototyping of the neuroprocessor was achieved using VHDL and the Altera Nios embedded system development kit. The FPGA-based prototype of the 10x10 UTM-Neuroprocessor is able to function at a frequency of 100 MHz and delivers performances up to 5.079 GCPS and 2.285 GCUPS. Software components, including a VB-based GUI, were also developed to allow execution of pattern recognition applications on the UTM-Neuroprocessor. For efficient VLSI implementation of the UTM-Neuroprocessor, the combined FPGA-VLSI approach was proposed. Correspondingly, the VLSI design of a 2x2 array computation engine, termed the Array_2x2 microchip, was developed in the AMI 0.5µm process technology and fabricated at the Europractice IC foundry. The fabricated Array_2x2 microchip can be applied to produce a 2x2 UTM-Neuroprocessor, in the combined FPGA-VLSI implementation approach. The design consumes an area of 16.9 mm2 on silicon and is encapsulated in 84-pin PGA package. SPICE simulations of the Array_2x2 design proved functionality at an operating frequency of 90 MHz. The microchip is able to deliver performances of up to 169.41 MCPS and 75.78 MCUPS MCUPS for a 2x2 UTM-Neuroprocessor