A broadband multilayer antireflection coating for thin film CdSeTe/CdTe solar cells

Thin film cadmium telluride (CdTe) photovoltaics (PV) is the most successful second-generation PV technology, with a current installed capacity of over 30 GWp, predominantly at utility scale. Recent improvements in the buffer layer of the device, switching from cadmium sulphide (CdS) to transparent magnesium-doped zinc oxide (MZO), tin oxide (SnO2), or zinc oxide (ZnO), and the addition of selenium to the absorber layer, have expanded the wavelength range over which CdTe devices operate, from 400–850 nm to 350–900 nm. These changes have resulted in higher efficiency devices. As a result, an optimized antireflection (AR) coating design is required to improve the efficiency further. A six-layer AR coating of SiO2 and ZrO2, building on a previous four-layer design for CdTe devices, has been designed, modeled, and fabricated on 3.8-mm thick fluorine-doped tin oxide coated TEC™15 substrates, reducing reflection by 3.38% absolute. Electrical measurements of a CdSeTe/CdTe device before and after addition of the AR coating show an increase in short-circuit current density (Jsc) of almost 1 mAcm−2, a relative increase of 3.45%, and a 0.6% increase in the conversion efficiency of the device, from 16.93% to 17.53%, which is a relative increase of 3.54%. Unlike conventional single layer AR coatings this multilayer coating is stable even under the high processing temperatures required in module manufacturing, so could be supplied by glass manufacturers. This newly optimized broadband AR coating on will enable significantly higher conversion efficiencies and help push CdSeTe/CdTe module efficiencies higher.</p

The effect of remnant CdSe layers on the performance of CdSeTe/CdTe photovoltaic devices

Thin film CdTe-based photovoltaic devices have achieved high efficiency above 22 %. The recent improvement in efficiency is due to Se alloying in the CdTe absorbers to form a CdSeTe/CdTe structure. The subsequent band gap grading increases the short circuit current density. The Se can be introduced by depositing a precursor thin film of either CdSe or a CdSeTe alloy and then diffusing the Se into the CdTe during the high temperature cadmium chloride activation process. Using CdSe is preferred because it is easier to control the Se concentration. However, during fabrication of the CdSeTe/CdTe devices, the CdSe thickness needs to be precisely controlled to prevent the retention of a CdSe remnant layer after the activation treatment. Retention of a remnant CdSe layer causes a dramatic reduction in device efficiency. In this work, we show that the reduction in efficiency is caused by a number of factors. The remnant CdSe layer is n-type which moves the position of the p-n junction. Also, it is widely thought that the CdSe remnants are photo-inactive. In this work, we clarify that the individual CdSe grains are actually highly photo-active. However, the grain sizes in the CdSe remnant and the adjacent CdSeTe layer are very small resulting in a high grain boundary area. Although the grain boundaries are passivated with chlorine, cathodoluminescence imaging and electrical measurements show that this is only partially effective. Also, EQE measurements show that the remnant CdSe causes parasitic absorption. Overall, the remnant CdSe layer causes a reduction in short circuit current density and device efficiency. The thickness of the CdSe precursor layer and the cadmium chloride activation process conditions must be precisely optimised to ensure that all the CdSe is consumed and inter-diffused to form the CdSeTe alloy for highest efficiency devices.</p