Eine Billion Operationen/s: Supercomputer

Über die Ergebnisse der vom Bundesministerium für Forschung und Technologie geförderten Forschung im Rahmen des MANNA-Supercomputer-Pilotprojekts wird berichtet. Das Projekt wird im GMD-Forschungsinstitut für Rechnerarchitektur und Softwaretechnik durchgeführt und erbrachte bereits Richtungsweisendes auf dem Gebiet der konfigurierbaren, massiv-parallelen Höchstleistungsrechnern. Die neuartige Rechnerarchitektur reicht vom Super-Arbeitsplatzrechner mit über einer Milliarde Operationen pro Sekunde bis zum massiv-parallelen Supercomputer mit 1 TeraFLOPS oder 10(exp 12) Operationen pro Sekunde. Die dafür nötigen neuen Rechnerarchitekturen werden beschrieben. Bisher ist allerdings die Programmierung durch den normalen Benutzer nicht möglich, da sie zu komplex ist. Die Entwicklung neuer Programmiermodelle ist daher vordringlichstes Forschungsthema. Ziel ist, daß sich der Supercomputer für den Anwender wie ein monolithischer Einzelrechner verhält. Über den Stand der Arbeiten auf dem Gebiet der Hardware und überblicksartig auch auf dem Gebiet der Software wird berichtet. Da es sich bei der neuen Architektur um eine Großzahl miteinander kooperierender Knotenrechner handelt (bis etwa 2400), ist den Kopplungsproblemen über das Verbindungsnetzwerk breiter Raum gegeben. Dem System liegt der superskalar-pipelined Intel 32/64-Bit-Prozessor i860XP zugrunde. VME-Anschlüsse sorgen für die Verbindung zur Außenwelt. Übergeordnetes Ziel des beschriebenen Forschungsprojekts ist es, die Parallelrechnerentwicklung mit neuen Ideen zu befruchten und dabei auch den Nachweis über Realisierbarkeit und Leistungsfähigkeit zu führen. Der vorliegende Artikel ist schwerpunktmäßig ein Bericht über den Hardwareteil des Projekts. Weitere Informationen lassen sich bei dem Forschungsinstitut GMD-First anfordern

PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620

The paper presents PowerMANNA- a distributed-memory parallel computer system based on the 64-Bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophisticated features of the MPC620 and incorporates important architectural concepts that allow us to exploit the performance of modern superscalar microprocessors in the context of massively parallel supercomputing. The two-way processor nodes of PowerMANNA are embedded in a powerful communication system supporting lowlatency communication and maximum connectivity. Processing and communication performance of an eight-node prototype are shown and compared with shared-memory machines and clusters. In the course of the presentation, experience gained with the PowerPC MPC620 processor is discussed

Analysis of bird data and derivation of design concepts for real time thermal disaster monitoring

An advanced Payload Data Handling (PDH) concept based on Commercial off the Shelf (COTS) components has been developed. The concept is built on Virtex-II Pro combined PowerPC and FPGA System on Chip (SoC) technology. The system can support Earth Observation mission data rates of up to 2.5 Gbps given present capabilities. This paper describes the on-board processing technology evaluation study and the COTS breadboard prototype development activity. The study used the Bi-spectral Infrared Detection (BIRD) satellite as a validated mission reference. The study evaluated BIRD on-board data processing technologies and assessed design concepts for future Earth Observation payload data processing applications. The PDH prototype development utilised the BIRD satellite design to cost philosophy comprising the use of COTS components supported by robust redundancy concepts and failure tolerance design approaches. The results of the paper study and breadboard development will be pre sented including the breadboard architectural design, redundancy concepts and the breadboard test set-up including a specifically designed demonstration application. First results from the Virtex-II Pro combined Power PC and FPGA SoC Single Event Effect (SEE) radiation tests will also be presented

PowerMANNA. A parallel architecture based on the PowerPC MPC620

The paper presents PowerMANNA - a distributed-memory parallel computer system based on the 64- bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophisticated features of the MPC620 and incorporates important architectural concepts that allow us to exploit the performance of modern superscalar microprocessors in the context of massively parallel supercomputing. The two-way processor nodes of PowerMANNA are embedded in a powerful communication system supporting low-latency communication and maximum connectivity. Processing and communication performance of an eight-node prototype are shown and compared with shared-memory machines and clusters. In the course of the presentation, experience obtained with the PowerPC MPC620 processor is discussed

Distributed On-board Computer System Prototype

Abstract: According to the project №2323 «The development of the prototype of distributed fault tolerant on board computing system for satellite control system and the complex of scientific equipment» of the International Scientific and Technical Center the work on development of software and hardware parts of mentioned prototype is carrying out in the Keldysh Institute of Applied Mathematics of RAS and the Space Research Institute of RAS together with the Fraunhofer institute Rechnerarchitektur und Softwaretechnik (FIRST, Berlin, Germany) develop software and hardware parts for the prototype. The preprint describes the project’s hardware part implemented by now. Analysis of requirements to the on-board control complex is adduced. Block structure and composition of small spacecraft base complex are considered. Architecture and block-scheme of on-board computing system are defined.Note: Research direction:Theoretical and applied problems of mechanic