Reducing the Error Floor of the Sign-Preserving Min-Sum LDPC Decoder via Message Weighting of Low-Degree Variable Nodes

Some low-complexity LDPC decoders suffer from error floors. We apply iteration-dependent weights to the degree-3 variable nodes to solve this problem. When the 802.3ca EPON LDPC code is considered, an error floor decrease of more than 3 orders of magnitude is achieve

DFE State-Tracking Demapper for Soft-Input FEC in 800G Data Center Interconnects

A simple one-step state model is used to track the DFE error propagation for 4-PAM. The knowledge of DFE output states is used to improve LLR accuracy. Demapping via DFE state tracking outperforms bit-interleaving and precoding schemes for the 802.3ca LDPC code by 0.76 dB

DFE State-Tracking Demapper for Soft-Input FEC in 800G Data Center Interconnects

A simple one-step state model is used to track the DFE error propagation for 4-PAM. The knowledge of DFE output states is used to improve LLR accuracy. Demapping via DFE state tracking outperforms bit-interleaving and precoding schemes for the 802.3ca LDPC code by 0.76 dB