6 research outputs found
Hungarian qubit assignment for optimized mapping of quantum circuits on multi-core architectures
Modular quantum computing architectures offer a promising alternative to monolithic designs for overcoming the scaling limitations of current quantum computers. To achieve scalability beyond small prototypes, quantum architectures are expected to adopt a modular approach, featuring clusters of tightly connected quantum bits with sparser connections between these clusters. Efficiently distributing qubits across multiple processing cores is critical for improving quantum computing systems’ performance and scalability. To address this challenge, we propose the Hungarian Qubit Assignment (HQA) algorithm, which leverages the Hungarian algorithm to improve qubit-to-core assignment. The HQA algorithm considers the interactions between qubits over the entire circuit, enabling fine-grained partitioning and enhanced qubit utilization. We compare the HQA algorithm with state-of-the-art alternatives through comprehensive experiments using both real-world quantum algorithms and random quantum circuits. The results demonstrate the superiority of our proposed approach, outperforming existing methods, with an average improvement of 1.28×.This work was supported in part by the European Research Council (ERC) under Grant 101042080 (WINC) and in part by the European Innovation Council (EIC) Pathfinder scheme under Grant 101099697 (QUADRATURE).Peer ReviewedPostprint (author's final draft
Mapping quantum algorithms to multi-core quantum computing architectures
Current monolithic quantum computer architectures have limited scalability.
One promising approach for scaling them up is to use a modular or multi-core
architecture, in which different quantum processors (cores) are connected via
quantum and classical links. This new architectural design poses new challenges
such as the expensive inter-core communication. To reduce these movements when
executing a quantum algorithm, an efficient mapping technique is required. In
this paper, a detailed critical discussion of the quantum circuit mapping
problem for multi-core quantum computing architectures is provided. In
addition, we further explore the performance of a mapping method, which is
formulated as a partitioning over time graph problem, by performing an
architectural scalability analysis
Characterizing the spatio-temporal qubit traffic of a quantum intranet aiming at modular quantum computer architectures
Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is crucial to develop tools that allow specific design space explorations. To this aim, in this paper we present a technique to perform a spatio-temporal characterization of quantum circuits running in multi-chip quantum computers. Specifically, we focus on the analysis of the qubit traffic resulting from operations that involve qubits residing in different cores, and hence quantum communication across chips, while also giving importance to the amount of intra-core operations that occur in between those communications. Using specific multi-core performance metrics and a complete set of benchmarks, our analysis showcases the opportunities that the proposed approach may provide to guide the design of multi-core quantum computers and their interconnects.Peer ReviewedPostprint (author's final draft
Mapping quantum circuits to modular architectures with QUBO
Modular quantum computing architectures are a promising alternative to
monolithic QPU (Quantum Processing Unit) designs for scaling up quantum
devices. They refer to a set of interconnected QPUs or cores consisting of
tightly coupled quantum bits that can communicate via quantum-coherent and
classical links. In multi-core architectures, it is crucial to minimize the
amount of communication between cores when executing an algorithm. Therefore,
mapping a quantum circuit onto a modular architecture involves finding an
optimal assignment of logical qubits (qubits in the quantum circuit) to
different cores with the aim to minimize the number of expensive inter-core
operations while adhering to given hardware constraints. In this paper, we
propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO)
technique to encode the problem and the solution for both qubit allocation and
inter-core communication costs in binary decision variables. To this end, the
quantum circuit is split into slices, and qubit assignment is formulated as a
graph partitioning problem for each circuit slice. The costly inter-core
communication is reduced by penalizing inter-core qubit communications. The
final solution is obtained by minimizing the overall cost across all circuit
slices. To evaluate the effectiveness of our approach, we conduct a detailed
analysis using a representative set of benchmarks having a high number of
qubits on two different multi-core architectures. Our method showed promising
results and performed exceptionally well with very dense and
highly-parallelized circuits that require on average 0.78 inter-core
communications per two-qubit gate.Comment: Submitted to IEEE QCE 202
Mapping quantum algorithms to multi-core quantum computing architectures
Current monolithic quantum computer architectures have limited scalability. One promising approach for scaling them up is to use a modular or multi-core architecture, in which different quantum processors (cores) are connected via quantum and classical links. This new architectural design poses new challenges such as the expensive inter-core communication. To reduce these movements when executing a quantum algorithm, an efficient mapping technique is required. In this paper, a detailed critical discussion of the quantum circuit mapping problem for multi-core quantum computing architectures is provided. In addition, we further explore the performance of a mapping method, which is formulated as a partitioning over time graph problem, by performing an architectural scalability analysis.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.QCD/Feld GroupQCD/Almudever LabQuantum Circuit Architectures and Technolog
Characterizing the spatio-temporal qubit traffic of a quantum intranet aiming at modular quantum computer architectures
Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is crucial to develop tools that allow specific design space explorations. To this aim, in this paper we present a technique to perform a spatio-temporal characterization of quantum circuits running in multi-chip quantum computers. Specifically, we focus on the analysis of the qubit traffic resulting from operations that involve qubits residing in different cores, and hence quantum communication across chips, while also giving importance to the amount of intra-core operations that occur in between those communications. Using specific multi-core performance metrics and a complete set of benchmarks, our analysis showcases the opportunities that the proposed approach may provide to guide the design of multi-core quantum computers and their interconnects. Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.QCD/Feld GroupQCD/Almudever LabQuantum Circuit Architectures and Technolog