INERD software: a new design tool to improve the robustness of RCMRF under Earthquake loading

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An All-Digital Single-Chip Symbol Synchronizer and Channel Decoder for DVB

In this contribution, design process and implementation of a single-chip timing and carrier synchronizer and channel decoder for digital video broadcasting over satellite (DVB-S) is described. The device consists of an A-to-D-converter with AGC, timing and carrier synchronizer including matched filter, Viterbi decoder including node synchronization, byte and frame synchronizer, convolutional de-interleaver, Reed Solomon decoder, and a descrambler. The system was designed in accordance with the DVB specifications. It is able to perform Viterbi decoding at data rates up to 56 Mbit/s and to sample the analog input values with up to 88 MHz. The chip allows automatic acquisition of the convolutional code rate and the position of the puncturing mask. The synchronization to the variable sample rates is performed fully digital by means of interpolation and controlled decimation. Hence, no external analog clock recovery circuit is needed. For algorithm design, system performance evaluation, and..

Feedforward Architectures for parallel Viterbi Decoding

The Viterbi-Algorithm (VA) is a common application of dynamic programming. Since it contains a nonlinear feedback loop (ACS-feedback, ACS: add-compare-select), this loop is the bottleneck in high data rate implementations. In this paper we show that asymptotically the ACS-feedback no longer has to be processed recursively, i.e. there is no feedback, resulting in negligible performance loss. This can be exploited to derive purely feedforward architectures for Viterbi decoding, such that a modular cascadable implementation results. By designing one cascadable module, any speedup can be achieved simply by adding modules to the implementation. It is shown that optimization criteria, e.g. minimum latency or maximum hardware efficiency, are met by very different architectures. be seen that they merge into a unique path, the optimum one. The survivor depth D is then defined as that depth in which it is highly probable that all paths merge (time k-D). In a practical implementation of the VA, called Viterbi decoder (VD), this allows the decoded transition to be given out with latency D. The computation of the best path to each node of the trellis is achieved through dynamic programming by calculating a path metric yi,k for each state Si at every time instant k according to the "ACS-recursion" v s.: yi,k+l = ma.ximum (,\.. y,k + 'j,k) V j+i which for the simple example Fig. 1 leads to 1