Hardware communication refinement in digital signal processing, modelling issues

In this paper we present the different modelling problems which a Digital Signal Processing (DSP) application designer has to tackle while refining an abstract specification relying on coarse grain data (e.g. matrices) toward a hardware implementation model relying on fine grain data (e.g. scalar). To address this problematic, we propose a modelling framework which can be used to refine an algorithm specified with coarse grain interfaces to a form which allow, from the functionnality point of view, to model all its fine grain hardware implmentation

Contributions à la modélisation et la simulation de niveau système des architectures matérielles-logicielles des systèmes embarqués.

This document presents my research activities since my recruitment at the University of Nantes in September 2004. These activities were successively carried out within the IREENA laboratory (Institute for Research in Electronics and Electrotechnics of Nantes Atlantique) until 2012, then within the IETR laboratory (Institute of Electronics and Digital Technologies). The scope of these activities corresponds to the design of hardware and software architectures of embedded electronic systems. In this context, my research activities have focused on the definition of methods favouring the modelling and simulation of hardware and software architectures in order to optimize them under time, cost and energy constraints.In this document, during the presentation of each of the covered topics, I report on the framework of this work, the nature of the contributions made and the approach undertaken. In doing so, I also explain my role in the supervision of the students who participated and contributed to this work and more broadly the collaborations set up. This synthesis tries to reconcile clarity and precision of the explanations. This document has three main parts. The first part corresponds to a detailed CV, summarizing in particular my professional experience with regard to the various activities carried out in research and teaching. The second part details in five chapters the research activities carried out since obtaining the doctoral degree, retracing the most significant results. Finally, the third part presents an assessment of the activities carried out and establishes a potential research program taking into account the identified prospects. Attached to this document is a detailed list of my publications

Contributions à la modélisation et la simulation de niveau système des architectures matérielles-logicielles des systèmes embarqués.

This document presents my research activities since my recruitment at the University of Nantes in September 2004. These activities were successively carried out within the IREENA laboratory (Institute for Research in Electronics and Electrotechnics of Nantes Atlantique) until 2012, then within the IETR laboratory (Institute of Electronics and Digital Technologies). The scope of these activities corresponds to the design of hardware and software architectures of embedded electronic systems. In this context, my research activities have focused on the definition of methods favouring the modelling and simulation of hardware and software architectures in order to optimize them under time, cost and energy constraints.In this document, during the presentation of each of the covered topics, I report on the framework of this work, the nature of the contributions made and the approach undertaken. In doing so, I also explain my role in the supervision of the students who participated and contributed to this work and more broadly the collaborations set up. This synthesis tries to reconcile clarity and precision of the explanations. This document has three main parts. The first part corresponds to a detailed CV, summarizing in particular my professional experience with regard to the various activities carried out in research and teaching. The second part details in five chapters the research activities carried out since obtaining the doctoral degree, retracing the most significant results. Finally, the third part presents an assessment of the activities carried out and establishes a potential research program taking into account the identified prospects. Attached to this document is a detailed list of my publications

Contributions à la modélisation et la simulation de niveau système des architectures matérielles-logicielles des systèmes embarqués.

This document presents my research activities since my recruitment at the University of Nantes in September 2004. These activities were successively carried out within the IREENA laboratory (Institute for Research in Electronics and Electrotechnics of Nantes Atlantique) until 2012, then within the IETR laboratory (Institute of Electronics and Digital Technologies). The scope of these activities corresponds to the design of hardware and software architectures of embedded electronic systems. In this context, my research activities have focused on the definition of methods favouring the modelling and simulation of hardware and software architectures in order to optimize them under time, cost and energy constraints.In this document, during the presentation of each of the covered topics, I report on the framework of this work, the nature of the contributions made and the approach undertaken. In doing so, I also explain my role in the supervision of the students who participated and contributed to this work and more broadly the collaborations set up. This synthesis tries to reconcile clarity and precision of the explanations. This document has three main parts. The first part corresponds to a detailed CV, summarizing in particular my professional experience with regard to the various activities carried out in research and teaching. The second part details in five chapters the research activities carried out since obtaining the doctoral degree, retracing the most significant results. Finally, the third part presents an assessment of the activities carried out and establishes a potential research program taking into account the identified prospects. Attached to this document is a detailed list of my publications

Timing correction technique for fast and accurate state-based performance models

International audienceEarly performance evaluation of embedded systemsextensively uses discrete-event simulation of high levelarchitecture models. Due to increasing complexity of systemarchitectures, simulation speed needs to be improved to guaranteeevaluation of candidate architectures in acceptable time. In thispaper, we introduce a timing correction technique that allowsthe number of processes managed by the simulation kernelto be reduced. The presented technique uses knowledge aboutapplication and platform to preserve accurate simulation resultsin case of contention at shared resources. We have implementedthis simulation technique into an industrial modeling framework.Our experiments show that a simulation speed-up by a factorof 7 can be achieved with no loss of accuracy. The proposedapproach has thus potential to improve the evaluation process ofarchitectures

A Hybrid Simulation Approach for Fast and Accurate Timing Analysis of Multi-Processor Platforms Considering Communication Resources Conflicts

International audienceIn the early design phase of embedded systems, discrete-event simulation is extensively used to analyse time properties of hardware-software architectures. Improvement of simulation efficiency has become imperative for tackling the ever increasing complexity of multi-processor execution platforms. The fundamental limitation of current discrete-event simulators lies in the time-consuming context switching required in simulation of concurrent processes. In this paper, we present a new simulation approach that reduces the number of events managed by a simulator while preserving timing accuracy of hardware-software architecture models. The proposed simulation approach abstracts the simulated processes by an equivalent executable model which computes the synchronization instants with no involvement of the simulation kernel. To consider concurrent accesses to platform shared resources, a correction technique that adjusts the computed synchronization instants is proposed as well. The proposed simulation approach was experimentally validated with an industrial modeling and simulation framework and we estimated the potential benefits through various case studies. Compared to traditional lock-step simulation approaches, the proposed approach enables significant simulation speed-up with no loss of timing accuracy. A simulation speed-up by a factor of 14.5 was achieved with no loss of timing accuracy through experimentation with a system model made of 20 functions, two processors and shared communication resources. Application of the proposed approach to simulation of a communication receiver model led to a simulation speed-up by a factor of 4 with no loss of timing accuracy. The proposed simulation approach has potential to support automatic generation of efficient system models

Etude, optimisation et implantation de systèmes MC-CDMA sur architectures hétérogènes

Afin de répondre aux besoins permanents de mobilité et de débit, l'émergence de la future quatrième génération de systèmes de radiocommunications repose autant sur le développement de nouvelles techniques de transmissions que sur la mise au point d'architectures matérielles performantes. Dans la recherche de modulations adaptées pour la couche physique de ces futurs réseaux, une approche pertinente repose sur la technique MC-CDMA, associant les techniques de modulations à porteuses multiples et l'étalement de spectre. Les travaux de recherche présentés dans cette thèse ont pour buts l'étude et la mise en œuvre pratique de systèmes de communications utilisant cette technique innovante. Notre travail a par ailleurs porté sur la définition et l'optimisation des méthodes de conception de tels systèmes vers des cibles architecturales hétérogènes.Après une présentation générale du contexte applicatif et des principes afférents aux systèmes MC-CDMA, un dimensionnement précis d'un tel système est présenté. Sa complexité et son intégration au sein d'une plate-forme de prototypage associant des composants DSP et FPGA sont analysées. Afin de proposer une démarche de conception efficace, nous envisageons l'application des méthodologies MCSE et AAA pour le développement du système MC-CDMA étudié. Une généralisation de l'approche AAA au cas des architectures hétérogènes est alors proposée. L'intérêt de ces méthodes pour l'optimisation de systèmes de transmissions reposant sur la technique MC-CDMA est ainsi démontrée.Modern communication networks are now confronted with increasing needs in terms of data rates and mobility. The development of the fourth generation relies on both new transmission techniques and on improved hardware architectures. The so-called MC-CDMA modulation scheme has recently emerged as one of the most promising technique for future networks physical layer. This thesis deals with the study and the implementation of MC-CDMA communication systems. It also considers the definition and the optimization of appropriate design methods on heterogeneous architectures.Following a general description of the context and of MC-CDMA related principles, a well-proportioned system is presented. Implementation complexity on a mixed DSP-FPGA prototyping board is then analysed. MCSE and AAA codesign methodologies are then considered for MC-CDMA system design. A generalization of the AAA methodology to heterogeneous architectures is proposed. The great interest of these methodologies for MC-CDMA systems optimization is then demonstrated.RENNES-INSA (352382210) / SudocSudocFranceF

Designing on heterogenous architecture : A3 methodology and syndex tool

International audienc

A Generic Executable Model for Fast Yet Accurate Contention Simulation in Multiprocessor Systems

International audienceWith an ever increasing complexity of hardware/software architectures, system-level simulation is intensivelyused to address the need for early performance evaluation. Inthis letter, we introduce a generic executable model that providesfast system simulation with preserved accuracy about sharedresource usage. The proposed executable model involves a limitednumber of simulation events by using instantaneous computationand retroactive correction methods of synchronisation instantsamong applications’ processes. We evaluated our approach onapplications with various numbers of tasks and different levelsof contention at shared resources. Our observations show thatwe can achieve the same accuracy with an average speedup of2.53 compared to traditional simulation approach

Mise en oeuvre de l'outil SynDex pour la conception et l'implantation de systèmes sur plate-forme hétérogène

International audienc