K→3πK\to 3 \pi decay results by NA48/2 at CERN SPS

The NA48/2 has collected the largest amount of $K\to3 \pi$. The charge asymmetry parameter $A_g$, sensitive to CP violation effects, has been measured with a precision of $10^{-4}$ (preliminary) both in the three charged pion mode ("charged" mode) and in the mode with two neutral pions in the final state ("neutral" mode). The Dalitz plot structure in the "neutral" mode will be discussed to point out the effects of the charged pion rescattering. The new preliminary measurement of the Dalitz plot parameters in the charged mode will be presentedComment: Proceedings prepared for HQL 06 conferenc

Search for Direct CP violation in charged Kaons with NA48/2 experiment

In questa tesi e’ discussa l’analisi dell’asimmetria della slope lineare in decadimenti dei kaoni carichi in tre pioni. In particolare e’ presentata l’analisi nel processo K->pi pi0 pi0. La misura di tale asimmetria e’ una misura dell’effetto di violazione diretta di CP nei kaoni carichi. Fino ad oggi la violazione di questa importante simmetria è stata stabilita soltanto nei mesoni neutri. Preziosi indicazioni sulla presenza di effetti provenienti da nuova fisica oltre il modello standard, potrebbe giungere da una misura del parametro Ag al livello di 10E-4 . Nel lavoro dopo una breve introduzione teorica, è descritta la tecnica sperimentale utilizzata nell’esperimento NA48/2 al CERN, la presa dati e la complessa strategia di misura con particolare enfasi sulle tecniche adottate per ridurre il contributo di effetti indotti da asimmetrie strumentali. Il risultato finale della tesi è oggetto di pubblicazione scientifica

NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems

We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.Comment: Proceedings for the 20th International Conference on Computing in High Energy and Nuclear Physics (CHEP

The FPGA based trigger and data acquisition system for the CERN NA62 experiment

The main goal of the NA62 experiment at CERN is to measure the branching ratio of the ultra-rare K+ → π+vv decay, collecting about 100 events to test the Standard Model of Particle Physics. Readout uniformity of sub-detectors, scalability, efficient online selection and lossless high rate readout are key issues. The TDCB and TEL62 boards are the common blocks of the NA62 TDAQ system. TDCBs measure hit times from sub-detectors, TEL62s process and store them in a buffer, extracting only those requested by the trigger system following the matching of trigger primitives produced inside TEL62s themselves. During the NA62 Technical Run at the end of 2012 the TALK board has been used as prototype version of the L0 Trigger Processor

A high-resolution TDC-based board for a fully digital trigger and data acquisition system in the NA62 experiment at CERN

A Time to Digital Converter (TDC) based system, to be used for most sub-detectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital Trigger and Data AcQuisition system (TDAQ), in which the TDC Board (TDCB) and a general-purpose motherboard (TEL62) will play a fundamental role. While TDCBs, housing four High Performance Time to Digital Converters (HPTDC), measure hit times from sub-detectors, the motherboard processes and stores them in a buffer, produces trigger primitives from different detectors and extracts only data related to the lowest trigger level decision, once this is taken on the basis of the trigger primitives themselves. The features of the TDCB board developed by the Pisa NA62 group are extensively discussed and performance data is presented in order to show its compliance with the experiment requirements.Comment: 6 pages, 7 figures, presented to IEEE RT 2014 Conference and I want to publish in TN

A multi-port 10GbE PCIe NIC featuring UDP offload and GPUDirect capabilities

NaNet-10 is a four-ports 10GbE PCIe Network Interface Card designed for low-latency real-time operations with GPU systems. To this purpose the design includes an UDP offload module, for fast and clock-cycle deterministic handling of the transport layer protocol, plus a GPUDirect P2P/RDMA engine for low-latency communication with NVIDIA Tesla GPU devices. A dedicated module (Multi-Stream) can optionally process input UDP streams before data is delivered through PCIe DMA to their destination devices, re-organizing data from different streams guaranteeing computational optimization. NaNet-10 is going to be integrated in the NA62 CERN experiment in order to assess the suitability of GPGPU systems as real-time triggers; results and lessons learned while performing this activity will be reported herein

Fast algorithm for real-time rings reconstruction

The GAP project is dedicated to study the application of GPU in several contexts in which real-time response is important to take decisions. The definition of real-time depends on the application under study, ranging from answer time of μs up to several hours in case of very computing intensive task. During this conference we presented our work in low level triggers [1] [2] and high level triggers [3] in high energy physics experiments, and specific application for nuclear magnetic resonance (NMR) [4] [5] and cone-beam CT [6]. Apart from the study of dedicated solution to decrease the latency due to data transport and preparation, the computing algorithms play an essential role in any GPU application. In this contribution, we show an original algorithm developed for triggers application, to accelerate the ring reconstruction in RICH detector when it is not possible to have seeds for reconstruction from external trackers