Analyzing the Logic Behavior of Digital CMOS Circuits in Presence of Simultaneous Switching Noise

International audienceThis paper analyzes the logic errors in digital circuits due to the presence of Simultaneous Switching Noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called ‘Minimum Switch Condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called ‘Signal Coherence Condition' is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunctio

Analyse de l'impact du bruit de commutation sur les blocs digitaux des circuits intégrés CMOS

MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF

On-Chip Monitor for the Detection of Logic Errors due to Simultaneous Switching Noise

International audienc