A high-density sea-of-gates architecture incorporating testability support

The authors describe an efficient and flexible CMOS sea-of-gates architecture for digital applications. This architecture supports the design of integrated circuits at all important physical design areas such as performance, implementation, and wiring. After a detailed discussion of the three architectural sublevels-performance, implementation, and wiring-the sea-of-gates architecture is presented. The functionality of this architecture is illustrated by describing the design of some benchmark circuit