High-voltage SiC power devices for improved energy efficiency

Silicon carbide (SiC) power devices significantly outperform the well-established silicon (Si) devices in terms of high breakdown voltage, low power loss, and fast switching. This review briefly introduces the major features of SiC power devices and then presents research works on breakdown phenomena in SiC pn junctions and related discussion which takes into account the energy band structure. Next, recent progress in SiC metal-oxide-semiconductor field effect transistors, which are the most important unipolar devices, is described with an emphasis on the improvement of channel mobility at the SiO2/SiC interface. The development of SiC bipolar devices such as pin diodes and insulated gate bipolar transistors, which are promising for ultrahigh-voltage (>10 kV) applications, are introduced and the effect of carrier lifetime enhancement is demonstrated. The current status of mass production and how SiC power devices can contribute to energy saving are also described

Epitaxial Growth of β-SiC on α-SiC Substrates by Chemical Vapor Deposition

Epitaxial growth of crystalline silicon carbide (SiC) on α-SiC substrates was carried out by chemical vapor deposition. β-SiC (3C-SiC) (111) can be epitaxially grown on a 15R-SiC (0001) substrate. The grown layers have far fewer DPBs (double positioning boundaries) than those on a 6H-SiC substrate. Successive etching of the grown layer revealed that the DPBs decreased as crystal growth proceeded. The decrease in DPBs was analyzed semi-quantitatively based on a model proposed by the authors, and the disappearance of DPBs was predicted. Schottky barrier diodes were fabricated on the grown layer and the electrical properties were investigated. The diode has a high breakdown voltage of 300V

Analytical model for reduction of deep levels in SiC by thermal oxidation

Two trap-reduction processes, thermal oxidation and C+ implantation followed by Ar annealing, have been discovered, being effective ways for reducing the Z[1/2] center (EC – 0.67 eV), which is a lifetime killer in n-type 4H-SiC. In this study, it is shown that new deep levels are generated by the trap-reduction processes in parallel with the reduction of the Z[1/2] center. A comparison of defect behaviors (reduction, generation, and change of the depth profile) for the two trap-reduction processes shows that the reduction of deep levels by thermal oxidation can be explained by an interstitial diffusion model. Prediction of the defect distributions after oxidation was achieved by a numerical calculation based on a diffusion equation, in which interstitials generated at the SiO2/SiC interface diffuse to the SiC bulk and occupy vacancies related to the origin of the Z[1/2] center. The prediction based on the proposed analytical model is mostly valid for SiC after oxidation at any temperature, for any oxidation time, and any initial Z[1/2]-concentration. Based on the results, the authors experimentally achieved the elimination of the Z[1/2] center to a depth of about 90 μm in the sample with a relatively high initial-Z[1/2]-concentration of 10[13] cm[−3] by thermal oxidation at 1400 °C for 16.5 h. Furthermore, prediction of carrier lifetimes in SiC from the Z[1/2] profiles was realized through calculation based on a diffusion equation, which considers excited-carrier diffusion and recombination in the epilayer, in the substrate, and at the surface

Measuring Terminal Capacitance and Its Voltage Dependency for High-Voltage Power Devices

The switching behavior of semiconductor devices responds to charge/discharge phenomenon of terminal capacitance in the device. The differential capacitance in a semiconductor device varies with the applied voltage in accordance with the depleted region thickness. This study develops a C - V characterization system for high-voltage power transistors (e.g., MOSFET, insulated gate bipolar transistor, and JFET), which realizes the selective measurement of a specified capacitance from among several capacitances integrated in one device. Three capacitances between terminals are evaluated to specify device characteristics-the capacitance for gate-source, gate-drain, and drain-source. The input, output, and reverse transfer capacitance are also evaluated to assess the switching behavior of the power transistor in the circuit. Thus, this paper discusses the five specifications of a C -V characterization system and its measurement results. Moreover, the developed C -V characterization system enables measurement of the transistor capacitances from its blocking condition to the conducting condition with a varying gate bias voltage. The measured C -V characteristics show intricate changes in the low-bias-voltage region, which reflect the device structure. The monotonic capacitance change in the high-voltage region is attributable to the expansion of the depletion region in the drift region. These results help to understand the dynamic behavior of high-power devices during switching operation

Depth profiles of electron and hole traps generated by reactive ion etching near the surface of 4H-SiC

Deep levels in the whole bandgap of 4H-SiC generated by reactive ion etching (RIE) are investigated with both n- and p-type SiC Schottky barrier diodes by deep-level transient spectroscopy (DLTS). Depth profiles of the observed deep levels were analyzed using the DLTS peak intensities at various bias voltages and numerical calculations. The major electron traps detected after RIE and subsequent annealing at 1300℃ include the Z₁⁄₂ (Ec-0.66eV), ON1 (Ec-0.88eV), ON2 (Ec-0.95eV), and EH₆⁄₇ (Ec-1.50eV) centers, and the major hole traps include the UK1 (Ev+0.51eV), UK2 (Ev+0.72eV), HK0 (Ev+0.77eV), HK2 (Ev+0.79eV), and HK3 (Ev+1.31eV) centers, where Ec and Ev denote the conduction and valence band edges, respectively. Most of the traps were localized near the surface (2 μm). By annealing at 1400℃, most of the hole traps were eliminated, but several electron traps remained. From these results, the origins of these defects are discussed