Packaging of surface active optoelectronic device arrays

Requirements of electronic systems are increasing, as the applications for these systems become more complex and require more bandwidth. Optical interconnection can help satisfy these system requirements. In order for an optical interconnect to be successful, system design must satisfy new demands on the packaging of the optically interconnected devices, different from those encountered in packaging electronic interconnects.This thesis addresses the issues faced in designing the packaging for a two-dimensional array of surface active optoelectronic devices, within the framework of a free-space optically interconnected backplane. Two demonstrator systems' packaging are presented, as well as a general discussion of the issues and constraints involved in the design, assembly and testing of this packaging. These issues include connectivity, bandwidth, thermal management, optomechanical interfacing and space constraints.The particular optoelectronic devices examined are Quantum Confined Stark Effect (QCSE) modulators and detectors. The impact of temperature sensitivity on these particular devices is examined, and a technique for optimizing their performance at a specific temperature is presented. As a thermal diagnostic aid, as well as a thermal management tool, the design and characterization of an array of temperature sensors integrated into an optoelectronic device array is presented

A Hybrid-SEED Smart Pixel Array for a Four-Stage Intelligent Optical Backplane Demonstrator

This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given