A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

We describe an effcient system-level simulator that, starting from the architecture of a well-specified transmissive medium (a channel modelled as single-ended or coupled differential microstrips plus cables) and including the system-level characteristics of transmitter and receiver (voltage swing, impedance, etc.), computes the eye diagram and the bit-error rate that is obtained in high-speed serial interfaces. Various equalization techniques are included, such as feed-forward equalization at the transmitter, continuous-time linear equalization and decision-feedback equalization at the receiver. The impact of clock and data jitter on the overall system performance can easily be taken into account and fully-adaptive equalization can be simulated without increasing the computational burden or the model\u2019s complexity

Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers

This work describes the design of a transmitter for a 10 Gbps serial interface to be used in automotive Electronic Control Units. The data rate is chosen in order to assess the design challenges in automotive environment at this frequency. The focus will be mainly on challenges related to transistor level design using a standard 28 nm technology, nevertheless a system level overview will be also given. The proposed transmitter features feed-forward equalization with 8 taps (1 pre-cursor and 6 postcursors, plus the main tap), whose strength is programmable with 16 discretization steps, optimizing the transmitter adaptability with reduced area. The proposed architecture is also able to tune its output impedance independently from the choice of the weights of the equalization tap. It features a 300 mV peak-topeak eye diagram with 16 equalization levels and achieves a remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit for the predriver+driver)

Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers

This paper presents the experimental characterization of a High-Speed Serial Interface (HSSI) for automotive microcontroller applications designed in 28 nm planar CMOS technology, verified over automotive corners and operating up to 11 Gb/s. The impedance of the full-rate voltage-mode transmitter can be tuned by activating several driver replicas. It also features an 8-tap Feed-Forward Equalizer (FFE) with taps programmable in steps of 1/16. The analog front-end of the receiver cascades a Variable-Gain Amplifier (VGA) and a Continuous-Time Linear Equalizer (CTLE), which can be individually tuned. The receiver is based on a half-rate architecture and features a 3-tap Decision-Feedback Equalizer (DFE), one tap being speculative to relax timing constraints; another VGA is embedded in the DFE summing node. The subsequent data and edge samplers are offset-compensated. The circuit is experimentally characterized over automotive corners at 6.25 Gb/s and 11 Gb/s on highly-reflecting PCB channels with up to 14.5 dB loss, demonstrating operations at bit-error ratio (BER) below 10 1212 up to 11 Gb/s. The HSSI occupies an area of 0.08 mm 2 and consumes 8.4 mW/Gb/s at 11 Gb/s and 6.2mW/Gb/s at 6.25 Gb/s

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

We describe an effcient system-level simulator that, starting from the architecture of a well-specified transmissive medium (a channel modelled as single-ended or coupled differential microstrips plus cables) and including the system-level characteristics of transmitter and receiver (voltage swing, impedance, etc.), computes the eye diagram and the bit-error rate that is obtained in high-speed serial interfaces. Various equalization techniques are included, such as feed-forward equalization at the transmitter, continuous-time linear equalization and decision-feedback equalization at the receiver. The impact of clock and data jitter on the overall system performance can easily be taken into account and fully-adaptive equalization can be simulated without increasing the computational burden or the model’s complexity