3D Printed structural electronics:embedding and connecting electronic components into freeform electronic devices

\u3cp\u3eThe need for personalised and smart products drives the development of structural electronics with mass-customisation capability. A number of challenges need to be overcome in order to address the potential of complete free form manufacturing of electronic devices. One key challenge is the integration of conductive structures and components into 3D printed devices by combining different materials and printing techniques that have nearly incompatible printing conditions. In this paper, several methods to integrate electronic circuits and components into a 3D printed structure are discussed. The functional performance of the resulting structures is described. Structural parts were manufactured with a stereolithography-based 3D printing technique, which was interrupted to pick and place electronic components, followed by either direct writing or squeegee filling of conductive material. A thermal curing step was applied to enhance the bonding and improve the electrical performance. Optical micrography, 4-point resistance measurement and cross-sectional analysis were performed to evaluate functionality.\u3c/p\u3

A common gate thin film transistor on poly(ethylene naphthalate) foil using step-and-flash imprint lithography

\u3cp\u3eIn this paper the fabrication of flexible thin film transistors (TFTs) on poly(ethylene naphthalate) foil is reported, with the source-drain layer patterned by step-and-flash imprint lithography (SFIL) as a first step towards fully UV-imprinted TFTs. The semiconductor was deposited by inkjet printing of a blend of TIPS-pentacene/polystyrene. The bottom contact, bottom gate TFTs were fabricated with the foil reversibly glued to a carrier, enhancing the dimensional stability and flatness of the foil to result in a thinner and more homogeneously distributed residual layer thickness. The obtained performance of the TFT devices, showing a mobility of μ = 0.56 cm\u3csup\u3e2\u3c/sup\u3e V\u3csup\u3e-1\u3c/sup\u3e s\u3csup\u3e-1\u3c/sup\u3e with an on/off ratio of >10\u3csup\u3e7\u3c/sup\u3e and near-zero threshold voltage, was found to be in good agreement with similar, photolithographically patterned state-of-the-art devices recently reported in literature. The results presented here show the feasibility of SFIL as a roll-to-roll compatible and down scalable patterning technique on flexible PEN foil for the fabrication of bottom-gate, bottom-contact flexible high-quality TFTs.\u3c/p\u3

Large-eddy simulation of dispersion from surface sources in arrays of obstacles

Towards meeting the objective of simulating heat transfer processes in urban areas, the study of dispersion from a scalar (ground) surface area source has been addressed as a first step, as dispersion from such a source is in some ways analogous to heat transfer from the surface. Two different urban-like geometries are considered in this study: an array with uniform height cubes and an array with random height cuboids. Some point measurement dispersion experiments in a wind tunnel have previously been carried out in identical arrays using a naphthalene sublimation technique. Large-eddy simulations (LES) of these experiments have been performed as a validation study and the details, presented here, demonstrate the influence of the roughness morphology on the dispersion processes and the power of LES for obtaining physically important scalar turbulent flux information