Should Illinois-scan based architectures be centralized or distributed?

This paper presents analysis of the trade off between hardware overhead, runtime, and test data volume when implementing systematic scan reconfiguration using centralized and distributed architectures of the segmented addressable scan, which is an Illinois-scan based architecture. The results show that the centralized scheme offers better data volume compression, similar ATPG runtime results and lower hardware overhead. The cost with the centralized scheme is in the routing congestion

Should Illinois-scan based architectures be centralized or distributed?

This paper presents analysis of the trade off between hardware overhead, runtime, and test data volume when implementing systematic scan reconfiguration using centralized and distributed architectures of the segmented addressable scan, which is an Illinois-scan based architecture. The results show that the centralized scheme offers better data volume compression, similar ATPG runtime results and lower hardware overhead. The cost with the centralized scheme is in the routing congestion

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10times to 40 times compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test set

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10times to 40 times compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test set