Importance sampling for high speed statistical Monte-Carlo simulations

As transistor dimensions of Static Random AccessMemory (SRAM) become smaller with each new technology generation, they become increasingly susceptible to statistical variations in their parameters. These statistical variations can result in failing memory. SRAM is used as a building block for the construction of large Integrated Circuits (IC). To ensure SRAM does not degrade the yield (fraction of functional devices) of ICs, very low failure probabilities of Pfail = 10-10 are strived for. For instance in SRAMmemory design one aims to get a 0.1% yield loss for 10Mbit memory, which means that 1 in 10 billion cells fails (Pfail = 10-10; this corresponds with an occurrence of -6.4s when dealing with a normal distribution). To simulate such probabilities, traditional Monte-Carlo simulations are not sufficient and more advanced techniques are required. Importance Sampling is a technique that is relatively easy to implement and provides sufficiently accurate results. Importance sampling is a well known technique in statistics to estimate the occurrences of rare events. Rare or extreme events can be associated with dramatic costs, like in finance or because of reasons of safety in environment (dikes, power plants). Recently this technique also received new attention in circuit design. Importance sampling tunes Monte Carlo to the area in parameter space from where the rare events are generated. By this a speed up of several orders can be achieved when compared to standard Monte Carlo methods. We describe the underlying mathematics. Experiments reveal the intrinsic power of the method. The efficiency of the method increases when the dimension of the parameter space increases. The method could be a valuable extension to the statistical capacities of any circuit simulator A Matlab implementation is included in the Appendix

A yield centric statistical design method for optimization of the SRAM active column

For robust design of SRAM memories, it is not sufficient to guarantee good statistical margins on the SRAM cell parameters. The sense amplifier needs sufficient input signal before it can reliably sense the data, while the SRAM cell requires sufficient time to develop that input signal. This paper presents a new statistical method that allows optimization of the access time of an SRAM memory, while guaranteeing a yield target set by the designer. Using this method, the access time of a high performance advanced CMOS SRAM has been improved 6%, while simultaneously reducing the sense amplifier siz

A yield centric statistical design method for optimization of the SRAM active column

For robust design of SRAM memories, it is not sufficient to guarantee good statistical margins on the SRAM cell parameters. The sense amplifier needs sufficient input signal before it can reliably sense the data, while the SRAM cell requires sufficient time to develop that input signal. This paper presents a new statistical method that allows optimization of the access time of an SRAM memory, while guaranteeing a yield target set by the designer. Using this method, the access time of a high performance advanced CMOS SRAM has been improved 6%, while simultaneously reducing the sense amplifier size

Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield

Variability is an important aspect of SRAM cell design. Failure probabilities of Pfail=10-10 have to be estimated through statistical simulations. Accurate statistical techniques such as Importance Sampling Monte Carlo simulations are essential to accurately and efficiently estimate such low failure probabilities. This paper shows that a simple form of Importance Sampling is sufficient for simulating Pfail=10-10 for the SRAM parameters Static Noise Margin, Write Margin and Read Current. For the SNM, a new simple technique is proposed that allows extrapolating the SNM distribution based on a limited number of trials. For SRAM total leakage currents, it suffices to take the averages into account for designing SRAM cells and modules. A guideline is proposed to ensure bitline leakage currents do not compromise SRAM functionality