Nitrogen transport and transformation in the Aberjona watershed

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Civil and Environmental Engineering, 2003.Includes bibliographical references (leaves [50]-[53]).The Aberjona watershed has been subject to contamination by dense urbanization and industrial effluent. A large amount of nitrogen loading to watersheds nation-widely comes from agricultural areas, but the Aberjona watershed has a considerable nitrogen inflow from .an industrial area. The nitrogen compounds in the Aberjona watershed might be delivered to the estuary near Boston, and could cause damage to the ocean environment. With these concerns in mind, the Aberjona watershed research team measured three kinds of nitrogen compounds and evaluated nitrogen characteristics in different regions. Enormous amount of ammonium has leached to the Aberjona River, one of the tributaries, as the river passes by an industrial area and two superfund sites. Horn Pond Creek, another tributary, has a low level of ammonium and nitrate flux, and dilutes the high concentration of ammonium from the Aberjona River before the creek arrives at the USGS site. In the Aberjona River, nitrification, which is an oxidization reaction from NH4+ to NO3 -, would be expected due to a high concentration of ammonium. In the Horn Pond Creek, denitrification, which is reduction reaction from NO3- to N2 , seems to take place between Horn Pond and Wedge Pond. As for organic nitrogen, it comprises around 15 %-30% of total nitrogen through the watershed.by Jongsok Choi.M.Eng

A Survey and Evaluation of FPGA High-Level Synthesis Tools

High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources

From Software Threads to Parallel Hardware with LegUp High-level Synthesis

High-level synthesis (HLS) can automatically synthesize software to hardware. With the design specification in software, HLS can reduce the lengthy design cycles of hardware, and make the performance and energy-efficiency benefits of hardware accessible to those without hardware skills. Since the introduction of the first C-based HLS tools more than a decade ago, however, the adaption of the technology has been slow by both software and hardware engineers. We attribute this to two key factors: 1) For hardware engineers, there is still a gap between HLS-generated hardware and human-designed hardware, partly due to the inability of HLS tools to fully exploit hardware parallelism, and 2) for software engineers, HLS remains to be a difficult endeavour, as many parts of the design, such as system integration, largely remain a manual process. This dissertation provides an HLS framework, LegUp, which seeks to address both issues. LegUp can compile an entire software program to hardware to produce a hardware-only system, or it can also automatically partition the program to generate a processor-accelerator hybrid system, wherein the compute-intensive program segments are accelerated by hardware, with the remaining segments executed in software on a processor. In both cases, a complete system is generated, including necessary memories and interconnect. To allow one to easily exploit hardware parallelism, we provide HLS support for synthesizing parallel software to parallel hardware. In particular, we support automatically compiling a multi-threaded program with Pthreads and OpenMP to parallel hardware accelerators that operate concurrently within a hardware-only or a processor-accelerator hybrid system. In the context of parallel hardware, we investigate architectural and memory optimizations that help to improve circuit performance and area, and discuss a method of using the producer-consumer pattern in software to infer a streaming circuit in hardware. With these techniques, we show that LegUp can produce high-performance hardware that can be competitive to circuits that are generated by commercial HLS tools, and demonstrate that LegUp-generated circuits can also outperform software executing on x86 processors.Ph.D

Enabling Hardware/Software Co-design in High-level Synthesis

A hardware implementation can bring orders of magnitude improvements in performance and energy consumption over a software implementation. Hardware design, however, can be extremely difficult. High-level synthesis, the process of compiling software to hardware, promises to make hardware design easier. However, compiling an entire software program to hardware can be inefficient. This thesis proposes hardware/software co-design, where computationally intensive functions are accelerated by hardware, while remaining program segments execute in software. The work in this thesis builds a framework where user-designated software functions are automatically compiled to hardware accelerators, which can execute serially or in parallel to work in tandem with a processor. To support multiple parallel accelerators, new multi-ported cache designs are presented. These caches provide low-latency high-bandwidth data to further improve the performance of accelerators. An extensive range of cache architectures are explored, and results show that certain cache architectures significantly outperform others in a processor/accelerator system.MAS

The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs

Abstract—We consider the impact of compiler optimizations on the quality of high-level synthesis (HLS)-generated FPGA hardware. Using a HLS tool implemented within the state-of-the-art LLVM [1] compiler, we study the effect of compiler optimiza-tions on the hardware metrics of circuit area, execution cycles, Fmax, and wall-clock time. We evaluate 56 different compiler optimizations implemented within LLVM and show that some optimizations significantly affect hardware quality. Moreover, we show that hardware quality is also affected by the order in which optimizations are applied. We then present a new HLS-directed approach to compiler optimizations, wherein we execute partial HLS and profiling at intermittent points in the optimization process and use the results to judiciously undo the impact of optimization passes predicted to be damaging to the generated hardware quality. Results show that our approach produces circuits with 16 % better speed performance, on average, versus using the standard-O3 optimization level. I