FPGA Design Techniques for Stable Cryogenic Operation

In this paper we show how a deep-submicron FPGA can be modified to operate at extremely low temperatures through modifications in the supporting hardware and in the firmware programming it. Though FPGAs are not designed to operate at a few Kelvin, it is possible to do so on virtue of the extremely high doping levels found in deep-submicron CMOS technology nodes. First, any PCB component, that does not conform with this requirement, is removed. Both the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad-hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA chip. The FPGA is powered with a supply at several meters distance, causing significant IR drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.Comment: The following article has been submitted to Review of Scientific Instruments. If it is published, it will be available on http://rsi.aip.or

Single Photon Imaging in CMOS

CMOS single photon detectors enable large pixel arrays and integrated ancillary circuits. As a consequence, higher timing accuracy and reduced power consumption can be achieved at lower costs. This paper discusses applications and implementation considerations to take into account when designing single photon imagers

Towards Large Scale CMOS Single-Photon Detector Arrays for Lab-on-Chip Applications

Single-photon detection is useful in many domains requiring time-resolved imaging, high sensitivity and high dynamic range. In this paper the miniaturization and performance potential of solid-state single-photon detectors are discussed in the context of lab-on-chip applications where high accuracy and/or high levels of parallelism are suited. Technological and design trade-offs are discussed in view of recent advances in integrated LED matrix technology and the emergence of new multiplication based architectures

3D Hand Model Fitting for Virtual Keyboard System

In this paper, a 3D hand model fitting method is presented which can recover the accurate finger positions for a virtual keyboard system. The 3D hand model consists of a detailed polygonal skin driven by an underlying skeleton system. The system uses a structured light sensor to generate dense range measurements of user’s hand motion. We exploit depth information and match it against the model to estimate the pose of the hand. The parameters for model deformation are optimized with the guide of the applied forces between model points and range measurements. To speed up the optimization, we simplify the physical model and apply hash table- based fast point pair matching. The system can be used in any application requiring zero formfactor and requires no contact with a medium. Examples of applications include virtual reality, gaming, design, etc

A Time-Gated 128x128 CMOS SPAD Array for on-Chip Fluorescence Detection

An all-digital, time-gated 128x128 CMOS image sensor for on-chip fluorescence detection is presented. The sensor pixel consists of a single-photon avalanche diode (SPAD), time gating circuitry and a 1bit memory. The sensor allows on-chip fluorescence detection and fluorescence lifetime imaging microscopy (FLIM) for on-chip molecular detection such as DNA, protein and cancer markers