Efficient Superconductor Arithmetic Logic Unit for Ultra-Fast Computing

We present a 4-bit Arithmetic Logic Unit (ALU) utilizing superconductor technology. The ALU serves as the central processing unit of a processor, performing crucial arithmetic and logical operations. We have adopted a bit-parallel architecture to ensure an efficient and streamlined design with minimal fanin/fanout and optimal latency. In terms of fabrication, the ALU has been fabricated using a standard commercial process. It operates at an impressive clock frequency exceeding 30 GHz while consuming a mere 4.75 mW of power, including applied reverse current, encompassing static and dynamic components. The ALU contains over 9000 Josephson junctions, with approximately 7000 JJs dedicated to wiring, delay lines, and path balancing, and it has over 18% bias margin. Designed as a co-processor, this arithmetic logic unit will work with external CMOS memory and processors via interface circuits. Thorough testing and validation of the ALU's functionality have been conducted with digital and analog simulations, and all the components were fabricated and measured within a 4K pulse-tube cryocooler. Experimental verification has confirmed the successful operation of both the arithmetic and logic units. These results have been analyzed and are presented alongside the experimental data to provide comprehensive insights into the ALU's behavior and capabilities.Comment: 11 pages, 10 figures and 37 reference

İnvestigation, modeling, and applications feasibility of the thermal crosstalk in high Tc transition edge bolometer arrays

Cataloged from PDF version of article.So far, the high Tc transition edge bolometer (TEB) devices are mostly used as single pixel detectors. Recently, there are a number of groups working on the 2-4 pixel array applications of the high Tc TEB. Though the target spectrum of the TEB is far IR and mm-waves, we are using a near IR laser source in our investigation due to practical reasons since the response analysis is similar. We have designed and implemented 4-pixel Y Ba2Cu3O7−δ (YBCO) edge transition bolometer arrays. The crosstalk study was made possible through the illumination of the sense-devices and measuring the voltage response of the blocked read-out device in the same array. This was done using a silver coated shadow mask. In order to prevent thermal artifacts created by the mask, the mask was made in free standing configuration on top of the devices. The devices were made of 200 nm and 400 nm thick pulsed laser deposited YBCO films on SrT iO3 and LaAl2O3 substrate materials. In this thesis, we made the qualitative investigation of the dependence of the thermal crosstalk on the various device parameters such as the substrate material, device layout, YBCO film thickness, operating temperature, and modulation frequency. Then, based on the experimental results, we proposed an analytical thermal model. We proposed two models: i) Basic model, which takes into account only the lateral heat diffusion in the substrate for quick design purposes ii)Analytical model, which takes into account the lateral heat diffusion, vertical heat diffusion, and the effect of the leaking laser radiation through the shadow mask, for detailed design purposes and verifying the qualitative analysis. Finally, we proposed and verified possible applications of the thermal crosstalk in TEB arrays. One proposed application of the crosstalk is the electrical free read-out of the sense pixels by utilization of the unique dependence of the magnitude and phase of the response on the thermal crosstalk between bolometer pixels in an array. The qualitative investigation made in this study is the most detailed investigation about the bolometer arrays and the proposed analytical model is the strongest among the reported ones so far in terms of fitting the experimental results, explaining the effects of the various parameters, and designing TEB arrays. The proposed crosstalk based read-out method is expected to decrease the read-out circuitry for possible TEB based applications. Since multilayer process is difficult to make in high Tc superconductors, decreasing the complexity of the read-out circuitry by half is even important and it is the first time that such a method is utilized including bolometer arrays made of different types of materials.Bozbey, AliPh.D

Hybrid Synaptic Structure for Spiking Neural Network Realization

Neural networks and neuromorphic computing play pivotal roles in deep learning and machine vision. Due to their dissipative nature and inherent limitations, traditional semiconductor-based circuits face challenges in realizing ultra-fast and low-power neural networks. However, the spiking behavior characteristic of single flux quantum (SFQ) circuits positions them as promising candidates for spiking neural networks (SNNs). Our previous work showcased a JJ-Soma design capable of operating at tens of gigahertz while consuming only a fraction of the power compared to traditional circuits, as documented in [1]. This paper introduces a compact SFQ-based synapse design that applies positive and negative weighted inputs to the JJ-Soma. Using an RSFQ synapse empowers us to replicate the functionality of a biological neuron, a crucial step in realizing a complete SNN. The JJ-Synapse can operate at ultra-high frequencies, exhibits orders of magnitude lower power consumption than CMOS counterparts, and can be conveniently fabricated using commercial Nb processes. Furthermore, the network's flexibility enables modifications by incorporating cryo-CMOS circuits for weight value adjustments. In our endeavor, we have successfully designed, fabricated, and partially tested the JJ-Synapse within our cryocooler system. Integration with the JJ-Soma further facilitates the realization of a high-speed inference SNN.Comment: 7 pages, 10 figure

Design and Implementation of a Single Flux Quantum Logic-Based Memory Controller for Josephson-CMOS Hybrid Memory Systems

Single flux quantum (SFQ) digital circuits have shown the potential for high speed/low power computation applications. Unfortunately, because of the low integration density and low driving capability of SFQ circuits, realizing large-scale memories by using only SFQ circuits is still a challenge. Josephson-CMOS hybrid memory, hybridizing high-speed, low power SFQ circuits, and high-densityCMOSmemories is already proposed as a solution to the large-scale memory problem in RSFQ digital systems. In this article, an SFQ-based memory controller which works up to 10 GHz clock frequencies is designed for Josephson-CMOS hybrid memory systems. The memory controller acts as a SFQ/CMOS interface between the SFQ circuit andSRAMmodule and generates the required waveforms for SRAM read and write operations. The circuit which has 4-b data and 2-b address lines is fabricated with AIST 2.5 kA/cm(2) STP2 process and operations of the circuits are verified. To demonstrate the scalability of the circuit, memory controller was scaled to 8-b data and 13-b address to control of the 64kb SRAM. Operations of the scaled memory controller are verified with analog simulations. Scaled circuit consumes 0.76 mW power in an area of 1.64 mm x 1.60 mm

Design of the Passive Transmission Lines for Different Stripline Widths and Impedances

In this paper, a practical method for designing of passive transmission lines (PTLs) in different widths ranging from 5 to 20 mu m with their respective driver and receiver circuits is demonstrated. The striplines were simulated with a microwave analyzing tool and their equivalent circuit models were extracted. Then, this model is used to design the driver and receiver circuits by analytical calculations. Circuits were fabricated at the AIST STP2 process and bias margins and bit error rates were measured in a closed cycle cryocooler system. In order to compensate the critical current's global shift in the fabrication, the tests were carried out in two different temperatures of 4.2 and 4.7 K. We have achieved 10% and 30% margins for receiver and driver circuits, respectively, for 20-mu m width striplines

Heat flux capacity measurement and improvement for the test of superconducting logic circuits in closed-cycle cryostats

With the current progress of superconducting integrated circuits, circuit complexities have reached more than 100,000 Josephson junctions. At the laboratory environment, circuit tests are generally being conducted at liquid Helium environments. With the commercialization of the superconducting integrated circuit-based systems and/or price increase of liquid Helium, utilization of the closed-cycle systems will be inevitable. Even though it is possible to implement closedcycle systems with quite substantial excess cooling powers after all the wirings and peripheral circuits, one point not to be overlooked is the power density at the superconducting chips. We have observed that the circuits designed for operation at liquid Helium bath have much higher power densities that exceed the heat flux capacities of closed-cycle cryocoolers. We have measured that the heat flux capacities of closed-cycle systems are about 0.1 W/cm(2) when the chip is in vacuum. Thus, if the power density in any of the bias resistors are higher than these values, it is difficult to keep the chip in superconducting state. With the positive feedback from a local hot spot under current bias, the chip rapidly heats up due to Joule heating. To increase the limit of power density, we propose an encapsulation method that increases the heat flux capacity of the system. With the encapsulation, the heat flux capacity of the system is increased to about 0.4 W/cm(2)

Modern aspects of Josephson dynamics and superconductivity electronics

In this book new experimental investigations of properties of Josephson junctions and systems are explored with the help of recent developments in superconductivity. The theory of the Josephson effect is presented taking into account the influence of multiband and anisotropy effects in new superconducting compounds. Anharmonicity effects in current-phase relation on Josephson junctions dynamics are discussed. Recent studies in analogue and digital superconductivity electronics are presented. Topics of special interest include resistive single flux quantum logic in digital electronics. Application of Josephson junctions in quantum computing as superconducting quantum bits are analyzed. Particular attention is given to understanding chaotic behaviour of Josephson junctions and systems. The book is written for graduate students and researchers in the field of applied superconductivity

Süperiletken Fraktal Mikroserit Yama Anten Tasarımı ve Benzetimi

26th IEEE Signal Processing and Communications Applications Conference (2018 : İzmir)Utilizing supercondutor thin-film materials for microstrip patch antennas leads significantly more efficient and electrically small antenna designs. Methods for estimating surface impedance and resonant frequencies of superconductor materials are given. Robust and more compact matching and feeding network techniques are described. Make use of an electromagnetic simulation tool for simulating antenna parameters. Fractal area reduction is applied and performances of antennas with different resonant frequencies are compared. © 2018 IEEE