Spin Correlations in the Geometrically Frustrated Pyrochlore Tb2Mo2O7

We report neutron scattering studies of the spin correlations of the geometrically frustrated pyrochlore Tb2Mo2O7 using single crystal samples. This material undergoes a spin-freezing transition below Tg~24 K, similar to Y2Mo2O7, and has little apparent chemical disorder. Diffuse elastic peaks are observed at low temperatures, indicating short-range ordering of the Tb moments in an arrangement where the Tb moments are slightly rotated from the preferred directions of the spin ice structure. In addition, a Q-independent signal is observed which likely originates from frozen, but completely uncorrelated, Tb moments. Inelastic measurements show the absence of sharp peaks due to crystal field excitations. These data show how the physics of the Tb sublattice responds to the glassy behavior of the Mo sublattice with the associated effects of lattice disorder.Comment: 4 pages, 4 figure

Eliminating speed penalty in ECC protected memories

ISBN 978-1-61284-208-0International audienceDrastic device shrinking, power supply reduction, increasing complexity and increasing operating speeds that accompanying technology scaling have reduced the reliability of nowadays ICs. The reliability of embedded memories is affected by particle strikes (soft errors), very low voltage operating modes, PVT variability, EMI and accelerated circuit aging. Error correcting codes (ECC) is an efficient mean for protecting memories against failures. A major issue with ECC is the speed penalty induced by the encoding and decoding circuits. In this paper we present an effective approach for eliminating this penalty and we demonstrate its efficiency in the case of an advanced reconfigurable OFDM modulator)

Towards a Tool for Implementing Delay-Free ECC in Embedded Memories

ISBN 978-1-4577-1953-0International audienceThe reliability of modern Integrated Circuits is affected by nanometric scaling. In many modern designs embedded memories occupy the largest part of the die and are designed as tight as allowed by the process. So they are more prone to failures than other circuits. Error correcting codes (ECC) are a convenient mean for protecting memories against failures. A major drawback of ECC is the speed penalty induced by the encoding and decoding circuits. In [5], we propose an architecture eliminating ECC delays in both read and write paths. However, this previous work does not describe a generic set of rules enabling inserting the delay-free ECC in any design. In this paper, we present the key points of an algorithm and a related tool automating its implementation

Using Error Correcting Codes without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study

Special Issue on Defect and Fault ToleranceInternational audienceDrastic device shrinking, power supply reduction, increasing complexity and increasing operating speeds affect adversely the reliability of nowadays Integrate Circuits (ICs). In many modern designs, embedded memories occupy the largest part of the die and comprise the large majority of transistors. Furthermore, memories are designed as tight as allowed by the process, and are therefore more prone to failures than other circuits. Error correcting codes (ECCs) are an efficient mean for protecting memories against failures. A major drawback of ECCs is the speed penalty induced by the encoding and decoding circuits. In this paper, we present an architecture enabling implementing ECCs without speed penalty. Furthermore, as the manual implementation of this solution is impractical for complex System-on-Chips (SoCs), we propose an algorithm and a set of generic rules allowing automatic insertion of the delay-free ECCs in any complex architecture at Register Transfer Level (RTL). With respect to a naive insertion in the design of the new architecture, the algorithm enable up to 20 % hardware reduction. The Finite State Machines (FSM) that controls the new ECC architecture is also generated automatically. Experimental evaluations show that the hardware overhead of the speed penalty free ECCs protected memory compared to a standard implementation of ECC protected memory is about 2.5 % with an additional power consumption of 6 %

Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance

International audienceIn nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons induce single-event upsets, affecting memory cells, latches, and flip-flops. They also induce single-event transients, initiated in the combinational logic and captured by the latches and flip-flops associated with the outputs of this logic. In the past, the major efforts were related on memories. However, as the whole situation is getting worse, solutions that protect the entire design are mandatory. Solutions for detecting the error in logic functions already exist, but there are only few solutions allowing the correction, leading to a lot of hardware overhead in nonprocessor design. In this paper, we present a novel technique that includes several hardware architectures and an algorithm for their implementations, which reduces the cost of rollback in any kinds of circuit

Robustesse des mémoires embarquées dans une architecture reconfigurable d un modulateur OFDM

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Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution

International audienceThe double sampling paradigm is an efficient method to protect the circuits against soft-errors. But the data that are going out of the area protected by double sampling are still vulnerable. In this paper we proposed an architectural solution that uses three latches to remove those constraints and protect the area outside the double sampling domain without adding a buffer stage