High Speed and Wide Bandwidth Delta-Sigma ADCs

This thesis describes the theory, design and implementation of a high-speed, high-performance continuous-time delta-sigma (CT??) ADC for applications such as medical imaging, high-definition video processing, and wireline and wireless communications. In order to achieve a GHz clocking speed, this thesis investigates excess loop delay compensation techniques at the system level which enable the design of a wide-bandwidth (BW), high-dynamic range (DR) CT?? modulator with good power-efficiency. This thesis demonstrates that CT?? ADCs implemented in nanometer CMOS are a power efficient alternative to Nyquist-rate ADCs for wide signal bandwidths (greater than 100MHz) and high dynamic ranges (more than 12-bit). The performance of a high-speed multi-bit CT?? modulator is often limited by the dynamic errors present in the feedback DAC. The applicable correction/calibration techniques are limited due to the modulator stability requirements. We have implemented a dynamic error correction technique which not only experimentally quantifies the level of dynamic errors but also improves the dynamic performance of the modulator.MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc

A 4 GHz Continuous-Time ΔΣ ADC With 70dB DR and -74dBFS THD in 125MHz BW

A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm 2 including the modulator, clock circuitry and decimation filter.Accepted Author ManuscriptElectronic Instrumentatio

A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic InstrumentationMicroelectronic

A 590 μw, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

This paper presents a continuous-Time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip occupies 0.36 mm2, achieves 107.2 dB SNR, 106.6 dB SNDR, and 107.3 dB dynamic range in a 24 kHz bandwidth while consuming 590 μW from a 1.8 V supply. This translates into a Schreier figure-of-merit (FoMs) of 183.4 dB and a FoMSNDR of 182.7 dB. Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic InstrumentationMicroelectronic

A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW

Advances in CMOS technologies have led to the development of continuous-time ΔΣ modulators (CTDSMs) with GHz sampling rates that achieve better than-100dBc linearity and bandwidths above 100MHz. However, at low frequencies (below 10MHz), their SNDR is limited by 1/f noise, which limits their use in radio receivers intended to cover both the AM and the FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/f noise, while maintaining interferer robustness, noise, spurious, and linearity performance. Implemented in a CTDSM sampling at 6GHz, it reduces its 1/f noise corner frequency by 22x and achieves -98.3dBc THD, 122dBFS SFDR in 120MHzBW. Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic InstrumentationMicroelectronic