A Ga-Sn Liquid Metal Mediated Structural Cathode for Li-O2 Batteries

One of the recent challenges in Li–O2 battery technology is the cycle life, which can be severely shortened by cathode passivation induced by discharge product accumulation; this can be eliminated by reducing the amount of discharge products. Herein, we report a feasibility study on the development of a Ga–Sn liquid metal (LM)-functionalized multiwalled carbon nanotubes (MWNTs) cathode. In a comparison of MWNT, LM, m-LM/MWNT (pre-mixed LM and MWNTs), and LM/MWNT (LM-modified MWNTs) cathodes, morphology analysis showed that small Li2O2 flakes rather than large crystals grow on the conductive Ga–Sn LM and MWNTs of the LM/MWNT cathode only. The decomposition of the flaky Li2O2 on the LM/MWNT cathode occurred at lower charge overpotentials, resulting in low polarization; thus, the cathode passivation and the consumption of the Li anode were both alleviated during the cyclic process. The LM/MWNT cathode significantly improved the cycle life, rate performance, and ultimate capacity of Li–O2 batteries

Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP

Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture are variable partitioning and scheduling. However, there’s little research work that has been done on these problems. In this paper, we present a new graph model for tackling the variable partitioning problem, namely, Variable Independence Graph (VIG), which provides more precise information for variable partitioning compared to the previous graph models. We also present a scheduling algorithm that takes advantages of multiple memory modules, Rotation Scheduling with Variable Re-partition (RSVR). It’s a new scheduling technique based on retiming and software pipelining. It may re-partition the variables if necessary during the scheduling process. The experiment results show that the average improvement on schedule length by using the algorithm is 44.8%. Another major contribution of this paper is that we invent an algorithm for design space exploration on multiple memory architecture. It produces more feasible solutions on a set of schedule length requirement. And our solution have less functional units that Interference Graph model.