16.2 Programming models and HW-SW Interfaces Abstraction for Multi-Processor SoC

For the design of classic computers the Parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to existing multiprocessor platforms using a low level software layer that implements the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs. Categories and Subject Descriptors C.3 [Special-purpose and application-based systems]: Real-time and embedded system

PPS: A Pipeline Path-based Scheduler

This paper presents a scheduling algorithm that im-proves on other approaches when dealing with the syn-thesis of control-flow dominated behavioral descrip-tions. It achieves this through the use of a constraint-driven path-based scheduling algorithm. The sub-optimality of the original path-based algorithms when dealing with loops is overcome through a new technique for pipelining different loop iterations during execution path generation. Results show that the algorithm al-ways generates the fastest solution in terms of clock cycles

Génération des Interfaces de Communication pour Systèmes Multiprocesseurs Monopuces : de la Spécification des Services de Communication vers l'Implémentation RTL

National audienc

Vers l'Automatisation de la Conception des Coprocesseurs de Communication pour les Systèmes Monopuces

National audienc

Formulation and evaluation of scheduling techniques for control flow graphs

Abstract This paper presents a theoretical basis for scheduling approaches based on purely control-ow graphs. This formulation includes a control ow graph model based on a nite discrete-time homogeneous Markov chain suitable to repesent complex control structures. A p r obabilistic nite state machine is introduced t o model the resulting schedule and evalute the eectiveness of the scheduling approaches for control ow graphs. The need of such models is imposed by the nature o f r e al time systems in which the control sequence depends on external conditions

Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design

In this paper, we propose a method of mixed-level cosimulation that enables gradual refinement of SoC communication from protocol-neutral communication to protocolfixed communication. For fine granularity in refinement, the method enables the designer to perform channel refinement and module refinement. Thus, the designer can perform more extensive design space exploration in communication refinement. We show the effectiveness of the proposed method in a case study of communication refinement in an IS-95 CDMA cellular phone system design

Timed HW-SW Cosimulation Using Native Execution of OS and Application SW

We present a method of timed HW-SW cosimulation which uses native execution of OS and application SW. The method presents fast and accurate cosimulation. Since the OS and application SW are executed natively on the simulation host, it gives faster simulation than the case when an instruction set simulator is used. Compared to the conventional usage of native execution of OS and application SW, it presents more accurate simulation since it allows for timing simulation of OS and application SW and it can be incorporated into timed HW-SW cosimulation. We present the details of building such a fast and accurate SW simulation mode