Design and distortion analysis of fully integrated image reject RF CMOS frontends

This thesis presents the design and experimental results of a 7.3GHz notch image reject filter, combined with a 5.8GHz low-noise amplifier (LNA), for integrated heterodyne receiver front-ends. A new image reject filter implementation is proposed. Q-enhancement circuitry for on-chip inductors are used to optimize the depth of image rejection. Experimental results show that more than 62dB of image rejection at 7.3GHz can be obtained in a standard CMOS 0.18mum technology, while operating from a 1.8V supply. The LNA exhibits a gain of 15.8dB and an IIP3 of -5.3dBm while consuming 9mW of power. With maximum image rejection, the LNA-notch combination circuit achieves a 4.1dB noise figure at 5.8GHz. The proposed notch filter alone can operate from a 1V supply voltage. It is shown analytically how circuit stability can be ensured.The implementation of new robust and stable high-Q CMOS image reject filters, which enables the realization of fully integrated heterodyne 5GHz RF receivers is also presented. A cascade of two notch filters with their image reject frequencies slightly offsetted is proposed, in order to obtain a wide image rejection bandwidth, without having to resort to the overhead of automatic tuning circuitry. Thus, power consumption, area, and complexity are significantly reduced. Experimental results show that more than 30d$ of image rejection can be obtained in a standard 0.18mum CMOS technology, over a 400MHz bandwidth centered at 7.4GHz

Log-domain filtering : disk-drive applications and distortion analysis

This thesis proposes a seventh-order 0.05° equiripple linear-phase continuous-time filter employing, for the first time, instantaneous companding. The filter was designed and integrated in a mature bipolar process. The amount of boost (up to 13dB) and group-delay adjustment (+/-30%) are digitally programmable. The DC gain is controllable up to 10dB, and the -3dB frequency (fc) is tunable from 5 to 70MHz. The output swing for 1% THD is higher than 100mVpp, with a 1.5V supply. The filter consumes very low power (5--13mW for fc = 70MHz), compared to state-of-the-art implementations (e.g. 120mW for fc = 100MHz [1]).An approach to estimate the distortion in log-domain filters is also presented. The models used for the bipolar transistors include the C pi and Csub parasitic capacitors, the beta effect, and the parasitic emitter resistances. Simple closed-form expressions describing the effect of each nonideality on distortion are derived and compared to simulations. A general method, which could be extended to analyze higher order filters, based on Volterra series, is used