Thermal Modeling of 3D Stacked MLC NAND Flash Memory

2

Hardware-Software Cosynthesis for Run-time Incrementally Reconfigurable FPGAs

1

Component-Based Design Approach for Multicore SoCs

1

A Practical Approach of Memory Access Parallelization to Exploit Multiple Off-chip DDR Memories

1

Selectively Protecting Error-Correcting Code for Area-Efficient and Reliable STT-RAM Caches

1

Synchronization Overhead Reduction in Timed Cosimulation

1

An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication

1

Mixed Integer Linear Programming-based Optimal Topology Synthesis of Cascaded Crossbar Switches

1