電化學陽極氧化法製備二氧化鈦薄膜

在電化學之陽極氧化鍍著二氧化鈦之研究中，文獻中陽極使用的皆是純鈦基材，因而限制了電化學法鍍著二氧化鈦薄膜的應用範圍。本研究主要的目的是以電化學法於異質的矽晶片基材上鍍著二氧化鈦薄膜，並與純鈦基材上結果比較，藉由詳細的製程監控與鍍膜分析，期望獲得高品質之二氧化鈦鍍膜。 實驗在室溫下1 M H2SO4鍍液中進行，以掃描電壓與定電壓模式 鍍著二氧化鈦薄膜於鈦箔與鍍鈦矽晶片上，同時並改變掃描電壓速率 及定電壓值，以探討鍍膜的成長與電壓大小的關係。鍍著結果經X光 繞射分析顯示，鈦箔在掃描0-100 V之鍍膜結晶結構為anatase與 rutile，鍍鈦矽晶片在掃描0-100 V之鍍膜結晶結構為anatase。鈦箔上 出現rutile之原因，可能是高電壓之驅動與火花放電產生之高熱，使 anatase部分相轉變為rutile。定電壓60 V以上，鈦箔表面即生成 anatase，鍍鈦矽晶片則在定電壓80 V以上生成anatase，此電壓值範 圍與兩基材在掃描0-100 V實驗中，電流產生振盪之電壓值範圍相 同，電流的振盪可能與陽極上產生介電崩潰有關，因此anatase可能 在電壓達崩潰電壓以上生成，而鍍鈦矽晶片上生成anatase之電壓值 較高可能是因基材之晶粒尺寸差異造成氧化進行所需之電壓不 同。拉曼光譜分析兩基材在掃描電壓與定電壓之鍍著結果，相當一致 顯示鍍膜表面均含有anatase相之結晶。所以兩基材在低於崩潰電壓 鍍著條件下，鍍膜厚度很薄，可能為非晶質結構之鈍態二氧化鈦膜。 高於崩潰電壓時，薄膜產生介電崩潰，陽極繼續反應並開始形成 anatase相之結晶，厚度隨電壓值升高而增加。以掃描式電子顯微鏡觀 察不同模式之鈦箔與鍍鈦矽晶片之鍍著結果，兩基材之鍍膜形貌上明 顯不同，可能由於鍍著過程中表面氧氣生成量的差異所致，造成鈦箔 上鍍膜易被氧氣撐破形成裂紋，而鍍鈦矽晶片上鍍膜則較緻密且無裂 紋產生。Concerning the anodic oxidation-based electrochemical synthesis of of TiO2 films, the material used for anode should be titanium. The main purpose of this research is to prepare TiO2 films on heterogeneous substrates such as Si instead of pure Ti by electrochemical oxidation and compare to the results on titanium substrates. Through the programmable control of the process and the analyses of the resultant thin films, we expect to obtain the high quality TiO2 thin films on Si substrates. The deposition has been performed at room temperature in 1 M H2SO4. Scanning voltage mode and constant potentiodynamic mode are used in the deposition of TiO2 thin films both on Ti and Ti/Si substrates. XRD results show that anatase and rutile phases of TiO2 were present on Ti foil whereas only anatase could be found on Ti/Si when both types of specimens were potentiodynamically scanned to 100 V with different scanning rates. When the electrolytic voltage is above 60 V using potentiodynamic mode, the surface of Ti foils exhibits an anatase phase. The anatase was formed on Ti/Si at a higher voltage of 80 V. Raman spectroscopy results also confirms the existence of the anatase phase on these two types of substrates.The resultant morphology of the films on the two types of substrates is also drastically different. The higher electrochemical surface activity and more rapid anodic reactions including the production of oxygen for Ti/Si substrates are the main causes of such differences.目錄 摘要 Abstract 第一章 緒論 1-1 研究背景………………………………………………..1 1-2 研究動機………………………………………………..2 1-3 研究目的………………………………………………..3 第二章 文獻回顧與理論背景 2-1 文獻回顧………………………………………………..5 2-2 理論背景………………………………………………10 第三章 研究方法 3-1 實驗流程……………………………………………....13 3-2 電化學沈積系統………………………………………13 3-3 基材之準備……………………………………………14 3-4 電化學鍍著……………………………………………16 3-5 分析儀器………………………………………………17 第四章 結果與討論 4-1 鍍著時電解電壓、電流與時間之關係……………..20 4-1-1 掃描電壓模式實驗……………………………….21 4-1-2 定電壓模式實驗………………………………….25 4-2 二氧化鈦鍍膜之外觀觀察與結晶構造之分析……..26 4-2-1 掃描電壓模式之鍍膜外觀分析………………….26 4-2-2 定電壓模式之鍍膜外觀分析…………………….27 4-2-3 掃描電壓模式鍍著之XRD分析………………...29 4-2-4 定電壓模式鍍著之XRD分析…………………...32 4-3 二氧化鈦鍍膜之微結構分析與元素成分分析..……34 4-3-1 掃描式電子顯微鏡分析………………………….34 4-3-2 鍍膜膜厚分析…………………………………….37 4-3-3 元素成分分析…………………………………….38 4-4 鍍膜化學組態分析…………………………………..41 4-5 熱氧化對照實驗結果(對照實驗)…………………...43 4-6 本實驗中氧化機構之探討…………………………..45 第五章 結論…………………………………………………...48 參考文獻……………………………………………………...5

Reaction kinetics at the interface of Ni-based under bump metallization in solder joints

近年來隨著CPU速度和功能的迅速增加，為了容納更高密度的I/O（Input/Output）數目在晶片上，每個銲料凸塊所承受的電流密度因此快速增加。截至2011年為止，每個銲料凸點的規模已經縮小至接近1~5微米的規模，而且逐年縮小的速度越來越快，因此在每個銲料凸塊上的電流密度將大幅增加，甚至超過10^6 × A/cm2以上。隨之而來產生熱和電遷移（EM）的效應，將對銲點的可靠度造成嚴峻考驗，因此如何選擇適當的表面覆晶金屬墊層是未來應用無鉛焊料的可靠度最主要的關注課題。 本篇論文中，我們藉由實驗結果嘗試找出鎳及鎳合金在銲點凸塊中的界面反應動力學機制。經由實驗的過程與反應動力學機制的推導，可以定義出鎳基金屬銲料凸塊中介金屬化合物成長的動力控制理論。在第三章中，我們成功的藉由液相電化學磊晶(LPEE)的方式製備出具優選方向的銅-錫合金化合物(Cu6Sn5)，經由實驗觀察並計算出鎳金屬原子在不同溫度下於銅錫合金化合物中的擴散係數，由擴散係數結果進一步計算，獲得不同鎳含量下的擴散活化能是隨著銅錫合金化合物的鎳含量增加而減少。經由進一步探討擴散係數與擴散活化能的變化與鎳含量的關係，我們發現兩者隨著銅錫合金化合物中鎳含量增加而減少的原因，主要與合金化合物的結晶相結構發生轉變的動力學機制有關。在第四章裡，我們探討了使用Fe-42Ni合金的LED導線架在浸潤(dipping)錫鉛(SnPb)銲料製程中發生的銲料脫銲(dewetting)機制，藉由脫銲機制理論推導出利用錫鉛銲料中加入微量的鎳以減緩金屬墊層與錫鉛銲料的界面反應，並探討延緩介金屬層成長過程的機制。 最後，在第五章裡我們依據前面各章節討論的機制，歸納出鎳基合金墊層在銲點凸塊中控制介金屬層生成的動力學成長機制，此研究結果可提供有效解決覆晶技術中焊點可靠度的課題參考。As the speed and functionality of CPUs rapidly increases in the past decades, a high density of flip-chip I/O (input/output) counts is required. By 2011, the size of flip-chip solder bumps had been approaching 1~5 µm and is expected to shrink faster than ever before, hence the current density in the flip-chip solder bumps will dramatically increase to over 10^6 A/cm2. Thermal and electron-migration (EM) effects bring the proper selection of the surface finishes for the soldering pads as one of the major concerns related to Pb-free solder joint reliability. In this thesis, we try to find out the interfacial reaction mechanism of Ni and Ni alloys in the solder joints by experiments. From the experimental results we are able to reveal the reaction kinetics that controls the intermetallics growth in the Ni-based solder bump pads. In Chapter 3, we describe the fabrication of preferred- orientation Cu6Sn5 crystals prepared by liquid phase electroepitaxy (LPEE). Also, we observed that the Ni interdiffusion coefficients in the Cu6Sn5 crystals at different annealing temperatures, and then yield the activation energy for Ni diffusion in the Cu6Sn5 crystals at different Ni content. It is found that as Ni diffuses into the ternary (Cu,Ni)6Sn5 compound phase, the activation energy of the Ni interdiffusion decreases with increasing Ni content because of the transformation of compound phase induced by Ni diffusion. The Ni interdiffusion mechanism and activation energy in binary Cu6Sn5 compound layer are accordingly dependent on the transformation of crystal structure in the host compounds. In Chapter 4, we discussed the mechanism of dewetting on Ag/Cu coated light emitting diode lead frames (LED LFs) (Fe-42Ni alloy) with SnPb immersion process. Then we discuss the mechanism that retards dewetting by Ni additives in the SnPb solder to slow down the soldering reaction and ease the ripening process. Finally in Chapter 5, based on the experimental results, we summarize the controlled reaction kinetics of the intermetallics on the Ni-based solder bump pads and propose a valuable reference to solve the reliability problems of the solder joints in flip-chip technology.Abstract in Chinese….....................................i Abstract.................................................iii List of Figures..................................................vii List of Tables....................................................xi Chapter 1 Introduction...............................................1 1-1 UBM with Ni layer in flip-chip solder joints .........1 1-2 Electromigration in flip-chip solder joint ...........7 1-3 Effect of Ni introduced into solder bump .…………….10 Chapter 2 Motivation ...............................................19 Chapter 3 Ni interdiffusion in Cu6Sn5....................23 3-1 Experimental ........................................23 3-2 Ni interdiffusion coefficient and activation energy in Cu6Sn5....................................................27 3-2-1 Ni interdiffusion coefficient.....................29 3-2-2 Kinetics of Ni interdiffusion.....................37 3-3 Summary .............................................43 Chapter 4 Dewetting Retardation on Ag/Cu Coated Light Emitting Diode Lead Frames during the Solder Immersion Process............44 4-1 Introduction ........................................44 4-2 Experimental ........................................47 4-3 SnPb solder immersion of Ag/Cu coating...............49 4-3-1 Spalling of intermetallic compounds...............49 4-3-2 Mechanisms for dewetting retardation..............57 4-4 Summary..............................................61 Chapter 5 Conclusion.....................................62 References ...............................................64 Vita and Publication List.................................6

一種光觸媒質子交換膜燃料電池及其製備方法

一種光觸媒質子交換膜燃料電池及其製備方法,使用光觸媒取代部分原先的碳黑觸媒載體,利用光觸媒受能量激發產生電子電洞對,同時對反應氣體進行催化,來增加整體觸媒的反應量,以提升其發電效率