1,343 research outputs found
The synthesis of a hardware scheduler for Non-Manifest Loops
This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near optimal scheduling-solutions for manifest loops, fail at scheduling non-manifest loops, since they lack the run time information needed which makes a static schedule feasible. In this paper a dynamic scheduling approach was chosen to circumvent this problem. We present a case study using VHDL where the focus lies on implementations with minimal memory usage and low communication overhead between various components of the architecture. This has resulted in an efficient and synthesisable system
Low-field diffusion magneto-thermopower of a high mobility two-dimensional electron gas
The low magnetic field diffusion thermopower of a high mobility
GaAs-heterostructure has been measured directly on an electrostatically defined
micron-scale Hall-bar structure at low temperature (T = 1.6 K) in the low
magnetic field regime (B < 1.2 T) where delocalized quantum Hall states do not
influence the measurements. The sample design allowed the determination of the
field dependence of the thermopower both parallel and perpendicular to the
temperature gradient, denoted respectively by Sxx (longitudinal thermopower)
and Syx (Nernst-Ettinghausen coefficient). The experimental data show clear
oscillations in Sxx and Syx due to the formation of Landau levels for 0.3 T < B
< 1.2 T and reveal that Syx is approximately 120 times larger than Sxx at a
magnetic field of 1 T, which agrees well with the theoretical prediction.Comment: 4 pages, 4 figure
Design citeria for applications with non-manifest loops
In the design process of high-throughput applications, design choices concerning the type of processor architecture and appropriate scheduling mechanism, have to be made. Take a reed-solomon decoder as an example, the amount of clock cycles consumed in decoding a code is dependent on the amount of errors within that code. Since this is not known in advance, and the environment in which the code is transmitted can cause a variable amount of errors within that code, a processor architecture which employs a static scheduling scheme, has to assume the worst case amount of clock cycles in order to cope with the worst case situation and provide correct results. On the other hand a processor that employs a dynamic scheduling scheme, can gain wasted clock cycles, by scheduling the exact amount of clock cycles that are needed and not the amount of clock cycles needed for the worst case situation. Since processor architectures that employ dynamic scheduling schemes have more overhead, designers have to make their choice beforehand. In this paper we address the problem of making the correct choice of whether to use a static or dynamic scheduling scheme. The strategy is to determine whether the application possess non-manifest behavior\ud
and weigh out this dynamic behavior against static scheduling solutions which were quite common in the past. We provide criteria for choosing the correct scheduling architecture for a high throughput application based upon the environmental and algorithm-specification constraints. Keywords¿ Non-manifest loop scheduling, variable latency functional units, dynamic hardware scheduling, self\ud
scheduling hardware units, optimized data-flow machine architecture
Zero field spin polarization in a 2D paramagnetic resonant tunneling diode
We study I-V characteristics of an all-II-VI semiconductor resonant tunneling
diode with dilute magnetic impurities in the quantum well layer. Bound magnetic
polaron states form in the vicinity of potential fluctuations at the well
interface while tunneling electrons traverse these interface quantum dots. The
resulting microscopic magnetic order lifts the degeneracy of the resonant
tunneling states. Although there is no macroscopic magnetization, the resulting
resonant tunneling current is highly spin polarized at zero magnetic field due
to the zero field splitting. Detailed modeling demonstrates that the local spin
polarization efficiency exceeds 90% without an external magnetic field.Comment: 7 pages, 10 figures (including supplementary information
Thermo-Electric Properties of Quantum Point Contacts
I. Introduction
II. Theoretical background (Landauer-Buttiker formalism of
thermo-electricity, Quantum point contacts as ideal electron waveguides,
Saddle-shaped potential)
III. Experiments (Thermopower, Thermal conductance, Peltier effect)
IV. ConclusionsComment: #4 of a series of 4 legacy reviews on QPC'
Lattice constant variation and complex formation in zincblende Gallium Manganese Arsenide
We perform high resolution X-ray diffraction on GaMnAs mixed crystals as well
as on GaMnAs/GaAs and GaAs/MnAs superlattices for samples grown by low
temperature molecular beam epitaxy under different growth conditions. Although
all samples are of high crystalline quality and show narrow rocking curve
widths and pronounced finite thickness fringes, the lattice constant variation
with increasing manganese concentration depends strongly on the growth
conditions: For samples grown at substrate temperatures of 220 and 270 degrees
C the extrapolated relaxed lattice constant of Zincblende MnAs is 0.590 nm and
0.598 nm respectively. This is in contrast to low temperature GaAs, for which
the lattice constant decreases with increasing substrate temperature.Comment: pdf onl
Spin Hall effects in HgTe Quantum Well Structures(Topological Aspects of Solid State Physics)
この論文は国立情報学研究所の電子図書館事業により電子化されました。研究会報
Streaming Reduction Circuit
Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths can be reduced by a pipelined commutative and associative binary operator in an efficient manner. The algorithm is simple to implement, has a low latency, produces results in-order, and requires only small buffers. Besides, it uses only a single pipeline for the involved operation. The complexity of the algorithm depends on the depth of the pipeline, not on the length of the input rows. In this paper we discuss an implementation of this algorithm and we prove its correctness
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