Hot-carrier-induced deep-level defects from gated-diode measurements on MOSFETs

The reverse-bias current in the gated-diode configuration of hot-carrier degraded MOS devices was measured. It is shown that interface defects created by the degradation contribute predominantly to the generation current. The spatial distribution of the deep-level defects was obtained by means of device simulation

The 'gated-diode' configuration in MOSFET's, a sensitive tool for characterizing hot-carrier degradation

This paper describes a new measurement technique, the forward gated-diode current characterized at low drain voltages to be applied in MOSFET's for investigating hot-carrier stress-induced defects at high spatial resolution. The generation/recombination current in the drain-to-substrate diode as a function of gate voltage, combined with two-dimensional numerical simulation, provides a sensitive tool for detecting the spatial distribution and density of interface defects. In the case of strong accumulation, additional information is obtained from interband tunneling processes occurring via interface defects. The various mechanisms for generating interface defects and fixed charges at variable stress conditions are discussed, showing that information complementary to that available from other methods is obtaine

Optimization and evaluation of variability in the programming window of a flash cell with molecular metal-oxide storage

We report a modeling study of a conceptual nonvolatile memory cell based on inorganic molecular metal-oxide clusters as a storage media embedded in the gate dielectric of a MOSFET. For the purpose of this paper, we developed a multiscale simulation framework that enables the evaluation of variability in the programming window of a flash cell with sub-20-nm gate length. Furthermore, we studied the threshold voltage variability due to random dopant fluctuations and fluctuations in the distribution of the molecular clusters in the cell. The simulation framework and the general conclusions of our work are transferrable to flash cells based on alternative molecules used for a storage media

A Hierarchical Model for CNT and Cu-CNT Composite Interconnects: From Density Functional Theory to Circuit-Level Simulations

No abstract available

Atoms-to-Circuits Simulation Investigation of CNT Interconnects for Next Generation CMOS Technology

In this study, we suggest a hierarchical model to investigate the electrical performance of carbon nanotube (CNT)- based interconnects. From the density functional theory, we have obtained important physical parameters, which are used in TCAD simulators to obtain the RC netlists. We then use these RC netlists for the circuit-level simulations to optimize interconnect design in VLSI. Also, we have compared various CNT-based interconnects such as single-walled CNTs, multi-walled CNTs, doped CNTs, and Cu-CNT composites in terms of conductivity, ring oscillator delay, and propagation time delay

Fast calculation of capacitances in silicon sensors with 3D and 2D numerical solutions of the Laplace's equation and comparison with experimental data and TCAD simulations

We have developed a software for fast calculation of capacitances in planar silicon pixel and strip sensors, based on 3D and 2D numerical solutions of the Laplace's equation. The validity of the 2D calculations was checked with capacitances measurements on Multi-Geometry Silicon Strip Detectors (MSSD). The 3D calculations were tested by comparison with pixel sensors capacitance measurements from literature. In both cases the Laplace equation results were compared with simulations obtained from the TCAD Sentaurus suite. The developed software is a useful tool for fast estimation of interstrip, interpixel and backplane capacitances, saving computation time, as a first approximation before using a more sophisticated platform for more accurate results if needed

Impact of randomly distributed dopants on Ω-gate junctionless silicon nanowire transistors

This paper presents experimental and simulation analysis of an Ω-shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/μm for 1.0 V and 2.52 mA/μm for the 1.8-V gate overdrive with an OFF-current set at 100 nA/μm. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current-voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean ID-VGs characteristic is in excellent agreement with the experimental measurements. Moreover, the mean ID-VGs characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs

Variability Study of High Current Junctionless Silicon Nanowire Transistors

Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits [1]. Fabricating a nanowire with characteristics required for a specific application, however, poses some challenges. For example, a major challenge is that as the transistors dimensions are reduced, it is difficult to maintain a low off-current (Ioff) whilst simultaneously maintaining a high on-current (Ion). This can be the result of quantum mechanical tunnelling, short channel effects or statistical variability [2]. A variety of new architectures, including ultra-thin silicon-on-insulator (SOI), double gate, FinFETs, tri-gate, junctionless and gate all-around (GAA) nanowire transistors, have therefore been developed to improve the electrostatic control of the conducting channel. This is essential since a low Ioff implies low static power dissipation and it will therefore improve power management in the multi-billion transistor circuits employed globally in microprocessors, sensors and memories

Interaction Between Precisely Placed Dopants and Interface Roughness in Silicon Nanowire Transistors: Full 3-D NEGF Simulation Study

In this work, we report a theoretical study based on quantum transport simulations that show the impact of the surface roughness on the performance of ultimately scaled gate-all-around silicon nanowire transistors (SNWT) with precisely positioned dopants designed for digital circuit applications. Due to strong inhomogeneity of the self-consistent electrostatic potential, a full 3-D real-space Non Equilibrium Green's Function (NEGF) formalism is used. The individual dopants and the profile of the channel surface roughness act as localized scatters and, hence, the impact on the electron transport is directly correlated to the combined effect of position of the single dopants and surface roughness shape. As a result, a large variation in the IOFF and ION and modest variation of the subthreshold slope are observed in the ID-VG characteristics when comparing devices without surface roughness. The variations of the current-voltage characteristics are analyzed with reference to the behaviour of the transmission coefficients, electron potential and electron concentration along the length of the device. Our calculations provide guidance for a future development of the next generation components with sub-10 nm dimensions for the semiconductor industry

Comparison between bulk and FDSOI POM flash cell: a multiscale simulation study

In this brief, we present a multiscale simulation study of a fully depleted silicon-on-insulator (FDSOI) nonvolatile memory cell based on polyoxometalates (POMs) inorganic molecular clusters used as a storage media embedded in the gate dielectric of flash cells. In particular, we focus our discussion on the threshold voltage variability introduced by random discrete dopants (random dopant fluctuation) and by fluctuations in the distribution of the POM molecules in the storage media (POM fluctuation). To highlight the advantages of the FDSOI POM flash cell, we provide a comparison with an equivalent cell based on conventional (BULK) transistors. The presented simulation framework and methodology is transferrable to flash cells based on alternative molecules used as a storage media