A CMOS image processing sensor for the detection of image features

A compact CMOS vision sensor for the detection of higher level image features, such as corners, junctions (T-, X-, Y-type) and linestops, is presented. The on-chip detection of these features significantly reduces the data amount and hence facilitates the subsequent processing of pattern recognition. The sensor performs a series of template matching operations in an analog/digital mixed mode for various kinds of image filtering operations including thinning, orientation decomposition, error correction, set operations, and others. The analog operations are done in the current domain. A design procedure, based on the formulation of the transistor mismatch, is applied to fulfill both accuracy and speed requirements. The architecture resembles a CNN-UM that can be programmed by a 30-bit word. The results of an experimental 16x16 pixel chip demonstrate that the sensor is able to detect features at high speed due to the pixel-parallel operation. Over 270 individual processing operations are performed in about 54 µsec

Extrapolating Analog-to-Digital Converter

We propose a new type of oversampled analog-to-digital converter. It uses digital extrapolators to predict the analog signal before it is converted, and a coarse quantizer to convert the prediction error. Such converters are expected to have reduced complexity in their analog circuitry, thanks to the processing in the digital domain. General linear extrapolation algorithms are derived from the spline theory, and can be easily implemented using digital filters. Simulations show that the speed-resolution trade-off is 2 bits per octave with simple linear extrapolation. Noise-shaping can be added using a matched analog preemphasis filter, in which case the converter behaves similar to a delta-sigma modulator of the same order

Biologically Inspired Vision Sensor for the Detection of Higher-Level Image Features

The paper briefly reviews certain aspects of the biological visual system and presents a smart vision sensor for the detection of higher-level features. The visual system processes information in a hierarchical manner starting from the retina up to the visual cortex. It decomposes the image in simple features (edges, orientation, line stops, corners, etc) using spatial and temporal information. At the higher level it integrates these primitive features, resulting in the recognition of complex objects. The sensor described in the paper is loosely modeled after the visual system and incorporates pixel level, programmable elements which extract orientation, end stops, corners and junctions from a line drawing. The architecture resembles a CNN-UM that can be programmed with a 30-bit word. The 16 x 16 pixels array detects these higher-level features in about 54 μseconds

Mixed-Signal Calibration of Pipelined Analog-Digital Converters

Least-Mean-Squares (LMS) based mixed-signal scheme for self-calibration of pipelined Analog-Digital Converter (ADC) is proposed. The technique uses an elegant continuous reference update algorithm to correct for gain errors and offset errors in a pipeline stage with minimal area and power overhead. Simulation results show the effeciency of the scheme for resolution of greater than 13bits in a CMOS process

A Low Distortion MOS Sampling Circuit

This paper presents a sampling technique with reduced distortion for use in a sample-and-hold circuit for high resolution analog-to-digital converters and switched capacitor filters. The technique involves bootstrapping both the gate and the bulk terminal of the sampling switch to improve linearity. Circuit implementation and SPICE level simulation results are presented

1.5-GHz CMOS Voltage-Controlled Oscillator Based on Thickness-Field-Excited Piezoelectric A1N Contour-Mode MEMS Resonators

This paper reports on the first demonstration of the 1.5 GHz CMOS oscillator based on thickness-field-excited (TFE) piezoelectric AIN MEMS contour-mode resonators (CMRs). The measured phase noise is -85 dBc/Hz at 10 kHz offset frequency and -151 dBc/Hz at 1MHz. This is the highest frequency MEMS oscillator ever reported using a laterally vibrating mechanical resonator. The high frequency operation has been enabled by optimizing the geometrical design and micro-fabrication process of TFE AIN CMRs, so that a low effective motional resistance around 50 Ω is achieved together with a high unloaded quality factor (Qu) approaching 2500 and simultaneously high kt2, up to 1.96%. A tunable-supply oscillator design is proposed for fine frequency tuning (or trimming) over a narrow bandwidth. Teh circuit design enables a novel GHz voltage-controlled oscillator (VCO) without the use of any low-Q tunable component. The 1.5 GHz VCO exhibits a 1500 ppm tuning range by a DC voltage change of 2.5 V. This technique can be utilized for fine frequency trimming and temperature compensation applications

1.05 GHz MEMS Oscillator Based On Lateral-Field-Excited Piezoelectric AlN Resonators

This paper reports on the first demonstration of a 1.05 GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric Aluminum Nitride (AlN) contour-mode resonators. The oscillator shows a phase noise level of –81 dBc/Hz at 1 kHz offset frequency and a phase noise floor of –146 dBc/Hz, which satisfies the GSM requirements of Ultra High Frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMIS 0.5 μm CMOS process, with the oscillator core consuming only 3.5 mW static power. A simple two-mask process was used to fabricate the LFE AlN resonators from 843 MHz to 1.64 GHz with high Q (up to 2,200) and kt2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make it suitable for post-CMOS integrated on-chip direct GHz frequency synthesis in reconfigurable multi-band wireless communications

Nonparallel Training for Voice Conversion Based on a Parameter Adaptation Approach

The objective of voice conversion algorithms is to modify the speech by a particular source speaker so that it sounds as if spoken by a different target speaker. Current conversion algorithms employ a training procedure, during which the same utterances spoken by both the source and target speakers are needed for deriving the desired conversion parameters. Such a (parallel) corpus, is often difficult or impossible to collect. Here, we propose an algorithm that relaxes this constraint, i.e., the training corpus does not necessarily contain the same utterances from both speakers. The proposed algorithm is based on speaker adaptation techniques, adapting the conversion parameters derived for a particular pair of speakers to a different pair, for which only a nonparallel corpus is available. We show that adaptation reduces the error obtained when simply applying the conversion parameters of one pair of speakers to another by a factor that can reach 30%. A speaker identification measure is also employed that more insightfully portrays the importance of adaptation, while listening tests confirm the success of our method. Both the objective and subjective tests employed, demonstrate that the proposed algorithm achieves comparable results with the ideal case when a parallel corpus is available

Low Fixed Pattern Noise Current-mode Imager Using Velocity Saturated Readout Transistors

This paper described a novel current-mode active pixel sensor (APS) imager. Conversion of photodiode voltage to output current is done using transistors operating in velocity saturation region. The high output impedance of this region makes it more suitable for current-sourcing operation than the linear region. The transistors also exhibit high linearity, allowing us to suppress fixed pattern noise (FPN) by correcting for both offset and gain variations among pixels. Experimental results on the fabricated 110×200 pixel array are presented. With conventional correlated double sampling (CDS), FPN is reduced from 3.8% to 0.85%. Further reduction requires compensation of gain variations, and results in a final FPN of 0.19%. A triple sampling approach is introduced to implement the described correction in hardware

A Spectral Conversion Approach to the Iterative Wiener Filter for Speech Enhancement

The Iterative Wiener Filter (IWF) for speech enhancement in additive noise is an effective and simple algorithm to implement. One of its main disadvantages is the lack of proper criteria for convergence, which has been shown to introduce severe degradation to the estimated clean signal. Here, an improvement of the IWF algorithm is proposed, when additional information is available for the signal to be enhanced. If a small amount of clean speech data is available, spectral conversion techniques can be applied for esimating the clean short-term spectral envelope of the speech signal from the noisy signal, with significant noise reduction. Our results show an average improvement compared to the original IWF that can reach 2 dB in the segmental output Signal-to-Noise Ratio (SNR), in low input SNR\u27s, which is perceptually significant